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Fixed a bug in opt_clean and some RTLIL API usage cleanups
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parent
d878fcbdc7
commit
dbb3556e3f
2 changed files with 14 additions and 13 deletions
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@ -37,20 +37,20 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
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SigPool used_signals;
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SigPool all_signals;
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for (auto &it : module->cells_)
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for (auto &conn : it.second->connections()) {
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if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
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for (auto cell : module->cells())
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for (auto &conn : cell->connections()) {
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if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first))
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driven_signals.add(sigmap(conn.second));
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if (!ct.cell_known(it.second->type) || ct.cell_input(it.second->type, conn.first))
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if (!ct.cell_known(cell->type) || ct.cell_input(cell->type, conn.first))
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used_signals.add(sigmap(conn.second));
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}
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for (auto &it : module->wires_) {
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if (it.second->port_input)
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driven_signals.add(sigmap(it.second));
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if (it.second->port_output)
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used_signals.add(sigmap(it.second));
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all_signals.add(sigmap(it.second));
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for (auto wire : module->wires()) {
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if (wire->port_input)
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driven_signals.add(sigmap(wire));
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if (wire->port_output)
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used_signals.add(sigmap(wire));
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all_signals.add(sigmap(wire));
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}
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all_signals.del(driven_signals);
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