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Fixed a bug in opt_clean and some RTLIL API usage cleanups

This commit is contained in:
Clifford Wolf 2014-07-27 13:19:05 +02:00
parent d878fcbdc7
commit dbb3556e3f
2 changed files with 14 additions and 13 deletions

View file

@ -37,20 +37,20 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
SigPool used_signals;
SigPool all_signals;
for (auto &it : module->cells_)
for (auto &conn : it.second->connections()) {
if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
for (auto cell : module->cells())
for (auto &conn : cell->connections()) {
if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first))
driven_signals.add(sigmap(conn.second));
if (!ct.cell_known(it.second->type) || ct.cell_input(it.second->type, conn.first))
if (!ct.cell_known(cell->type) || ct.cell_input(cell->type, conn.first))
used_signals.add(sigmap(conn.second));
}
for (auto &it : module->wires_) {
if (it.second->port_input)
driven_signals.add(sigmap(it.second));
if (it.second->port_output)
used_signals.add(sigmap(it.second));
all_signals.add(sigmap(it.second));
for (auto wire : module->wires()) {
if (wire->port_input)
driven_signals.add(sigmap(wire));
if (wire->port_output)
used_signals.add(sigmap(wire));
all_signals.add(sigmap(wire));
}
all_signals.del(driven_signals);