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Enabled AST/Verilog front-end optimizations per default

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This commit is contained in:
Clifford Wolf 2013-06-10 13:19:04 +02:00
parent af79b4bd98
commit db98a18edb
5 changed files with 30 additions and 11 deletions
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2
frontends/ast/simplify.cc
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@ -797,7 +797,7 @@ skip_dynamic_range_lvalue_expansion:;
if (0) { case AST_REDUCE_XOR: const_func = RTLIL::const_reduce_xor; }
if (0) { case AST_REDUCE_XNOR: const_func = RTLIL::const_reduce_xnor; }
if (0) { case AST_REDUCE_BOOL: const_func = RTLIL::const_reduce_bool; }
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
if (children[0]->type == AST_CONSTANT) {
RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), dummy_arg, children[0]->is_signed, false, -1);
newNode = mkconst_bits(y.bits, false);
}