mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00
Code Activity

ice40_dsp: fix typo

Browse source
This commit is contained in:
Eddie Hung 2020-01-17 16:08:04 -08:00
parent e17f3f8c63
commit db68e4c2a7
2 changed files with 13 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

11
tests/arch/xilinx/xilinx_dsp.ys Normal file
View file

@ -0,0 +1,11 @@
read_verilog <<EOT
module top(input [24:0] a, input [17:0] b, output [42:0] o1, o2, o5);
DSP48E1 m1 (.A(a), .B(16'd1234), .P(o1));
assign o2 = a * 16'd0;
wire [42:0] o3, o4;
DSP48E1 m2 (.A(a), .B(b), .P(o3));
assign o4 = a * b;
DSP48E1 m3 (.A(a), .B(b), .P(o5));
endmodule
EOT
xilinx_dsp