mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 17:44:09 +00:00
Code Activity

Add test for shifting by INT_MAX

Browse source 
Currently resulting in CI failing on main during fsm checks which generate a circuit that simplifies to this.
This commit is contained in:
Krystine Sherwin 2025-02-14 13:28:24 +13:00
parent df3c62a4ed
commit db5b76edc1
No known key found for this signature in database
1 changed files with 9 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
tests/opt/opt_expr_shr_int_max.ys Normal file
View file

@ -0,0 +1,9 @@
read_verilog << EOF
module uut_00034(b, y);
input signed [30:0] b;
output [11:0] y = b >> ~31'b0; // shift by INT_MAX
endmodule
EOF
# This should succeed, even with UBSAN halt_on_error
opt_expr