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Added buffer detection to "abc -lut"

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This commit is contained in:
Clifford Wolf 2015-09-18 20:12:56 +02:00
parent 745d56149d
commit db548800b6
1 changed files with 6 additions and 0 deletions
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6
passes/techmap/abc.cc
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@ -1075,6 +1075,12 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
design->select(module, cell); design->select(module, cell);
continue; continue;
} }
if (c->type == "$lut" && GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) {
SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)];
SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)];
module->connect(my_y, my_a);
continue;
}
RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type); RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
cell->parameters = c->parameters; cell->parameters = c->parameters;