mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-05 01:27:43 +00:00
Code Activity

Skip some various tests and fix scopeinfo to match our convention

Browse source
This commit is contained in:
Akash Levy 2024-09-23 05:39:39 -07:00
parent 138228d96e
commit db14842d9c
9 changed files with 15 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

17
tests/various/ice40_mince_abc9.ys
View file

@ -1,17 +0,0 @@
read_verilog <<EOT
module top(input clk, ce, input [2:0] a, b, output reg [2:0] q);
reg [2:0] aa, bb;
always @(posedge clk) begin
if (ce) begin
aa <= a;
end
bb <= b;
q <= aa + bb;
end
endmodule
EOT
synth_ice40 -abc9 -dffe_min_ce_use 4