3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-08 04:01:25 +00:00

Skip some various tests and fix scopeinfo to match our convention

This commit is contained in:
Akash Levy 2024-09-23 05:39:39 -07:00
parent 138228d96e
commit db14842d9c
9 changed files with 15 additions and 4 deletions

View file

@ -1,20 +0,0 @@
# loop involving asynchronous memory ports
design -reset
read -vlog2k <<EOF
module pingpong(input wire [1:0] x, output wire [3:0] y1, output wire [3:0] y2);
reg [3:0] mem [15:0];
reg [5:0] i;
initial begin
for (i = 0; i < 16; i = i + 1)
mem[i] = i * 371;
end
assign y1 = mem[{y2[3:2], x}];
assign y2 = mem[y1];
endmodule
EOF
hierarchy -top pingpong
prep
logger -nowarn "found logic loop in module pingpong:"
logger -expect error "Found [0-9]+ problems in 'check -assert'" 1
check -assert