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test: add test for #2014

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Eddie Hung 2020-05-02 14:22:37 -07:00
parent 2285cf1219
commit db13852ed6
1 changed files with 12 additions and 0 deletions
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tests/various/bug2014.ys Normal file
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@ -0,0 +1,12 @@
read_verilog <<EOT
module test (
input signed [1:0] n,
output [3:0] dout
);
assign dout = n + 4'sd 4;
endmodule
EOT
alumacc
select -assert-count 1 t:$alu
equiv_opt -assert opt -fine