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https://github.com/YosysHQ/yosys
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Add utility module for representing flip-flops.
This commit is contained in:
Marcelina Kościelnicka
parent
eae2edf3e4
commit
dafe04d559
2 changed files with 441 additions and 0 deletions
1
Makefile
1
Makefile
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@ -585,6 +585,7 @@ $(eval $(call add_include_file,kernel/modtools.h))
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$(eval $(call add_include_file,kernel/macc.h))
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$(eval $(call add_include_file,kernel/utils.h))
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$(eval $(call add_include_file,kernel/satgen.h))
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$(eval $(call add_include_file,kernel/ff.h))
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$(eval $(call add_include_file,kernel/ffinit.h))
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$(eval $(call add_include_file,libs/ezsat/ezsat.h))
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$(eval $(call add_include_file,libs/ezsat/ezminisat.h))
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440
kernel/ff.h
Normal file
440
kernel/ff.h
Normal file
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@ -0,0 +1,440 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef FF_H
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#define FF_H
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#include "kernel/yosys.h"
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#include "kernel/ffinit.h"
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YOSYS_NAMESPACE_BEGIN
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struct FfData {
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FfInitVals *initvals;
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SigSpec sig_q;
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SigSpec sig_d;
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SigSpec sig_clk;
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SigSpec sig_en;
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SigSpec sig_arst;
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SigSpec sig_srst;
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SigSpec sig_clr;
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SigSpec sig_set;
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bool has_d;
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bool has_clk;
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bool has_en;
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bool has_srst;
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bool has_arst;
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bool has_sr;
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bool ce_over_srst;
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bool is_fine;
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bool pol_clk;
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bool pol_en;
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bool pol_arst;
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bool pol_srst;
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bool pol_clr;
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bool pol_set;
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Const val_arst;
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Const val_srst;
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Const val_init;
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Const val_d;
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bool d_is_const;
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int width;
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dict<IdString, Const> attributes;
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FfData(FfInitVals *initvals, Cell *cell = nullptr) : initvals(initvals) {
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width = 0;
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has_d = true;
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has_clk = false;
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has_en = false;
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has_srst = false;
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has_arst = false;
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has_sr = false;
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ce_over_srst = false;
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is_fine = false;
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pol_clk = false;
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pol_en = false;
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pol_arst = false;
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pol_srst = false;
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pol_clr = false;
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pol_set = false;
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d_is_const = false;
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if (!cell)
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return;
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sig_q = cell->getPort(ID::Q);
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width = GetSize(sig_q);
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attributes = cell->attributes;
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if (initvals)
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val_init = (*initvals)(sig_q);
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std::string type_str = cell->type.str();
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if (cell->type.in(ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr))) {
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if (cell->type == ID($sr)) {
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has_d = false;
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} else {
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sig_d = cell->getPort(ID::D);
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}
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if (!cell->type.in(ID($ff), ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr))) {
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has_clk = true;
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sig_clk = cell->getPort(ID::CLK);
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pol_clk = cell->getParam(ID::CLK_POLARITY).as_bool();
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}
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if (cell->type.in(ID($dffe), ID($dffsre), ID($adffe), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($dlatchsr))) {
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has_en = true;
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sig_en = cell->getPort(ID::EN);
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pol_en = cell->getParam(ID::EN_POLARITY).as_bool();
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}
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if (cell->type.in(ID($dffsr), ID($dffsre), ID($dlatchsr), ID($sr))) {
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has_sr = true;
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sig_clr = cell->getPort(ID::CLR);
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sig_set = cell->getPort(ID::SET);
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pol_clr = cell->getParam(ID::CLR_POLARITY).as_bool();
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pol_set = cell->getParam(ID::SET_POLARITY).as_bool();
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}
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if (cell->type.in(ID($adff), ID($adffe), ID($adlatch))) {
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has_arst = true;
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sig_arst = cell->getPort(ID::ARST);
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pol_arst = cell->getParam(ID::ARST_POLARITY).as_bool();
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val_arst = cell->getParam(ID::ARST_VALUE);
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}
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if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce))) {
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has_srst = true;
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sig_srst = cell->getPort(ID::SRST);
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pol_srst = cell->getParam(ID::SRST_POLARITY).as_bool();
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val_srst = cell->getParam(ID::SRST_VALUE);
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ce_over_srst = cell->type == ID($sdffce);
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}
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} else if (cell->type == ID($_FF_)) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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} else if (type_str.substr(0, 5) == "$_SR_") {
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is_fine = true;
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has_d = false;
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has_sr = true;
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pol_set = type_str[5] == 'P';
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pol_clr = type_str[6] == 'P';
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sig_set = cell->getPort(ID::S);
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sig_clr = cell->getPort(ID::R);
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} else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 8) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[6] == 'P';
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sig_clk = cell->getPort(ID::C);
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} else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 10) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[7] == 'P';
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sig_clk = cell->getPort(ID::C);
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has_en = true;
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pol_en = type_str[8] == 'P';
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sig_en = cell->getPort(ID::E);
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} else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 10) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[6] == 'P';
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sig_clk = cell->getPort(ID::C);
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has_arst = true;
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pol_arst = type_str[7] == 'P';
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sig_arst = cell->getPort(ID::R);
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val_arst = type_str[8] == '1' ? State::S1 : State::S0;
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} else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 12) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[7] == 'P';
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sig_clk = cell->getPort(ID::C);
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has_arst = true;
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pol_arst = type_str[8] == 'P';
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sig_arst = cell->getPort(ID::R);
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val_arst = type_str[9] == '1' ? State::S1 : State::S0;
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has_en = true;
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pol_en = type_str[10] == 'P';
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sig_en = cell->getPort(ID::E);
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} else if (type_str.substr(0, 8) == "$_DFFSR_" && type_str.size() == 12) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[8] == 'P';
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sig_clk = cell->getPort(ID::C);
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has_sr = true;
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pol_set = type_str[9] == 'P';
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pol_clr = type_str[10] == 'P';
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sig_set = cell->getPort(ID::S);
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sig_clr = cell->getPort(ID::R);
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} else if (type_str.substr(0, 9) == "$_DFFSRE_" && type_str.size() == 14) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[9] == 'P';
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sig_clk = cell->getPort(ID::C);
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has_sr = true;
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pol_set = type_str[10] == 'P';
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pol_clr = type_str[11] == 'P';
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sig_set = cell->getPort(ID::S);
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sig_clr = cell->getPort(ID::R);
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has_en = true;
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pol_en = type_str[12] == 'P';
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sig_en = cell->getPort(ID::E);
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} else if (type_str.substr(0, 7) == "$_SDFF_" && type_str.size() == 11) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[7] == 'P';
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sig_clk = cell->getPort(ID::C);
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has_srst = true;
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pol_srst = type_str[8] == 'P';
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sig_srst = cell->getPort(ID::R);
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val_srst = type_str[9] == '1' ? State::S1 : State::S0;
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} else if (type_str.substr(0, 8) == "$_SDFFE_" && type_str.size() == 13) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[8] == 'P';
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sig_clk = cell->getPort(ID::C);
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has_srst = true;
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pol_srst = type_str[9] == 'P';
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sig_srst = cell->getPort(ID::R);
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val_srst = type_str[10] == '1' ? State::S1 : State::S0;
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has_en = true;
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pol_en = type_str[11] == 'P';
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sig_en = cell->getPort(ID::E);
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} else if (type_str.substr(0, 9) == "$_SDFFCE_" && type_str.size() == 14) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[9] == 'P';
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sig_clk = cell->getPort(ID::C);
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has_srst = true;
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pol_srst = type_str[10] == 'P';
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sig_srst = cell->getPort(ID::R);
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val_srst = type_str[11] == '1' ? State::S1 : State::S0;
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has_en = true;
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pol_en = type_str[12] == 'P';
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sig_en = cell->getPort(ID::E);
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ce_over_srst = true;
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} else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 11) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_en = true;
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pol_en = type_str[9] == 'P';
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sig_en = cell->getPort(ID::E);
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} else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 13) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_en = true;
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pol_en = type_str[9] == 'P';
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sig_en = cell->getPort(ID::E);
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has_arst = true;
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pol_arst = type_str[10] == 'P';
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sig_arst = cell->getPort(ID::R);
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val_arst = type_str[11] == '1' ? State::S1 : State::S0;
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} else if (type_str.substr(0, 11) == "$_DLATCHSR_" && type_str.size() == 15) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_en = true;
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pol_en = type_str[11] == 'P';
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sig_en = cell->getPort(ID::E);
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has_sr = true;
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pol_set = type_str[12] == 'P';
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pol_clr = type_str[13] == 'P';
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sig_set = cell->getPort(ID::S);
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sig_clr = cell->getPort(ID::R);
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} else {
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log_assert(0);
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}
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if (has_d && sig_d.is_fully_const()) {
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d_is_const = true;
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val_d = sig_d.as_const();
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if (has_en && !has_clk && !has_sr && !has_arst) {
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// Plain D latches with const D treated specially.
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has_en = has_d = false;
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has_arst = true;
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sig_arst = sig_en;
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pol_arst = pol_en;
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val_arst = val_d;
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}
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}
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}
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// Returns a FF identical to this one, but only keeping bit indices from the argument.
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FfData slice(const std::vector<int> &bits) {
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FfData res(initvals);
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res.sig_clk = sig_clk;
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res.sig_en = sig_en;
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res.sig_arst = sig_arst;
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res.sig_srst = sig_srst;
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res.has_d = has_d;
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res.has_clk = has_clk;
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res.has_en = has_en;
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res.has_arst = has_arst;
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res.has_srst = has_srst;
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res.has_sr = has_sr;
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res.ce_over_srst = ce_over_srst;
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res.is_fine = is_fine;
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res.pol_clk = pol_clk;
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res.pol_en = pol_en;
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res.pol_arst = pol_arst;
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res.pol_srst = pol_srst;
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res.pol_clr = pol_clr;
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res.pol_set = pol_set;
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res.attributes = attributes;
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for (int i : bits) {
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res.sig_q.append(sig_q[i]);
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if (has_d)
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res.sig_d.append(sig_d[i]);
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if (has_sr) {
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res.sig_clr.append(sig_clr[i]);
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res.sig_set.append(sig_set[i]);
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}
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if (has_arst)
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res.val_arst.bits.push_back(val_arst[i]);
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if (has_srst)
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res.val_srst.bits.push_back(val_srst[i]);
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res.val_init.bits.push_back(val_init[i]);
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}
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res.width = GetSize(res.sig_q);
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// Slicing bits out may cause D to become const.
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if (has_d && res.sig_d.is_fully_const()) {
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res.d_is_const = true;
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res.val_d = res.sig_d.as_const();
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}
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return res;
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}
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Cell *emit(Module *module, IdString name) {
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if (!width)
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return nullptr;
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if (!has_d && !has_sr) {
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if (has_arst) {
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// Convert this case to a D latch.
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has_d = has_en = true;
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has_arst = false;
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sig_d = val_arst;
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sig_en = sig_arst;
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pol_en = pol_arst;
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} else {
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// No control inputs left. Turn into a const driver.
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initvals->remove_init(sig_q);
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module->connect(sig_q, val_init);
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return nullptr;
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}
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}
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initvals->set_init(sig_q, val_init);
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Cell *cell;
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if (!is_fine) {
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if (!has_d) {
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log_assert(has_sr);
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cell = module->addSr(name, sig_set, sig_clr, sig_q, pol_set, pol_clr);
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} else if (!has_clk && !has_en) {
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log_assert(!has_arst);
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log_assert(!has_srst);
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log_assert(!has_sr);
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cell = module->addFf(name, sig_d, sig_q);
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} else if (!has_clk) {
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log_assert(!has_srst);
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if (has_sr)
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cell = module->addDlatchsr(name, sig_en, sig_set, sig_clr, sig_d, sig_q, pol_en, pol_set, pol_clr);
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else if (has_arst)
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cell = module->addAdlatch(name, sig_en, sig_arst, sig_d, sig_q, val_arst, pol_en, pol_arst);
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else
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cell = module->addDlatch(name, sig_en, sig_d, sig_q, pol_en);
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} else {
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if (has_sr) {
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if (has_en)
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cell = module->addDffsre(name, sig_clk, sig_en, sig_set, sig_clr, sig_d, sig_q, pol_clk, pol_en, pol_set, pol_clr);
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else
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cell = module->addDffsr(name, sig_clk, sig_set, sig_clr, sig_d, sig_q, pol_clk, pol_set, pol_clr);
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} else if (has_arst) {
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if (has_en)
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cell = module->addAdffe(name, sig_clk, sig_en, sig_arst, sig_d, sig_q, val_arst, pol_clk, pol_en, pol_arst);
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else
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cell = module->addAdff(name, sig_clk, sig_arst, sig_d, sig_q, val_arst, pol_clk, pol_arst);
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} else if (has_srst) {
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if (has_en)
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if (ce_over_srst)
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cell = module->addSdffce(name, sig_clk, sig_en, sig_srst, sig_d, sig_q, val_srst, pol_clk, pol_en, pol_srst);
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else
|
||||
cell = module->addSdffe(name, sig_clk, sig_en, sig_srst, sig_d, sig_q, val_srst, pol_clk, pol_en, pol_srst);
|
||||
else
|
||||
cell = module->addSdff(name, sig_clk, sig_srst, sig_d, sig_q, val_srst, pol_clk, pol_srst);
|
||||
} else {
|
||||
if (has_en)
|
||||
cell = module->addDffe(name, sig_clk, sig_en, sig_d, sig_q, pol_clk, pol_en);
|
||||
else
|
||||
cell = module->addDff(name, sig_clk, sig_d, sig_q, pol_clk);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (!has_d) {
|
||||
log_assert(has_sr);
|
||||
cell = module->addSrGate(name, sig_set, sig_clr, sig_q, pol_set, pol_clr);
|
||||
} else if (!has_clk && !has_en) {
|
||||
log_assert(!has_arst);
|
||||
log_assert(!has_srst);
|
||||
log_assert(!has_sr);
|
||||
cell = module->addFfGate(name, sig_d, sig_q);
|
||||
} else if (!has_clk) {
|
||||
log_assert(!has_srst);
|
||||
if (has_sr)
|
||||
cell = module->addDlatchsrGate(name, sig_en, sig_set, sig_clr, sig_d, sig_q, pol_en, pol_set, pol_clr);
|
||||
else if (has_arst)
|
||||
cell = module->addAdlatchGate(name, sig_en, sig_arst, sig_d, sig_q, val_arst.as_bool(), pol_en, pol_arst);
|
||||
else
|
||||
cell = module->addDlatchGate(name, sig_en, sig_d, sig_q, pol_en);
|
||||
} else {
|
||||
if (has_sr) {
|
||||
if (has_en)
|
||||
cell = module->addDffsreGate(name, sig_clk, sig_en, sig_set, sig_clr, sig_d, sig_q, pol_clk, pol_en, pol_set, pol_clr);
|
||||
else
|
||||
cell = module->addDffsrGate(name, sig_clk, sig_set, sig_clr, sig_d, sig_q, pol_clk, pol_set, pol_clr);
|
||||
} else if (has_arst) {
|
||||
if (has_en)
|
||||
cell = module->addAdffeGate(name, sig_clk, sig_en, sig_arst, sig_d, sig_q, val_arst.as_bool(), pol_clk, pol_en, pol_arst);
|
||||
else
|
||||
cell = module->addAdffGate(name, sig_clk, sig_arst, sig_d, sig_q, val_arst.as_bool(), pol_clk, pol_arst);
|
||||
} else if (has_srst) {
|
||||
if (has_en)
|
||||
if (ce_over_srst)
|
||||
cell = module->addSdffceGate(name, sig_clk, sig_en, sig_srst, sig_d, sig_q, val_srst.as_bool(), pol_clk, pol_en, pol_srst);
|
||||
else
|
||||
cell = module->addSdffeGate(name, sig_clk, sig_en, sig_srst, sig_d, sig_q, val_srst.as_bool(), pol_clk, pol_en, pol_srst);
|
||||
else
|
||||
cell = module->addSdffGate(name, sig_clk, sig_srst, sig_d, sig_q, val_srst.as_bool(), pol_clk, pol_srst);
|
||||
} else {
|
||||
if (has_en)
|
||||
cell = module->addDffeGate(name, sig_clk, sig_en, sig_d, sig_q, pol_clk, pol_en);
|
||||
else
|
||||
cell = module->addDffGate(name, sig_clk, sig_d, sig_q, pol_clk);
|
||||
}
|
||||
}
|
||||
}
|
||||
cell->attributes = attributes;
|
||||
return cell;
|
||||
}
|
||||
};
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue