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xilinx: Test our DSP48A/DSP48A1 simulation models.
This commit is contained in:
Marcin Kościelnicki
parent
aa1adb0f1e
commit
dadaf7ed78
5 changed files with 362 additions and 7 deletions
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@ -2099,7 +2099,7 @@ always @* begin
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2'b00: XMUX <= 0;
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2'b01: XMUX <= M;
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2'b10: XMUX <= P;
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2'b11: XMUX <= {D_OUT[11:0], B1_OUT, A1_OUT};
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2'b11: XMUX <= {D_OUT[11:0], A1_OUT, B1_OUT};
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default: XMUX <= 48'hxxxxxxxxxxxx;
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endcase
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end
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@ -2117,8 +2117,8 @@ end
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// The post-adder.
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wire signed [48:0] X_EXT;
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wire signed [48:0] Z_EXT;
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assign X_EXT = XMUX;
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assign Z_EXT = ZMUX;
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assign X_EXT = {1'b0, XMUX};
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assign Z_EXT = {1'b0, ZMUX};
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assign {CARRYOUT_IN, P_IN} = OPMODE_OUT[7] ? (Z_EXT - (X_EXT + CARRYIN_OUT)) : (Z_EXT + X_EXT + CARRYIN_OUT);
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// Cascade outputs.
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4
techlibs/xilinx/tests/.gitignore
vendored
4
techlibs/xilinx/tests/.gitignore
vendored
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@ -8,4 +8,8 @@ dsp_work*/
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test_dsp_model_ref.v
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test_dsp_model_uut.v
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test_dsp_model
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test_dsp48a_model_ref.v
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test_dsp48a1_model_ref.v
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test_dsp48a1_model_uut.v
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test_dsp48a1_model
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*.vcd
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17
techlibs/xilinx/tests/test_dsp48a1_model.sh
Normal file
17
techlibs/xilinx/tests/test_dsp48a1_model.sh
Normal file
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@ -0,0 +1,17 @@
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#!/bin/bash
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set -ex
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if [ -z $ISE_DIR ]; then
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ISE_DIR=/opt/Xilinx/ISE/14.7
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fi
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sed 's/DSP48A1/MARKER1/; s/DSP48A/DSP48A_UUT/; s/MARKER1/DSP48A1_UUT/; /module DSP48A_UUT/,/endmodule/ p; /module DSP48A1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp48a1_model_uut.v
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if [ ! -f "test_dsp48a1_model_ref.v" ]; then
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cp $ISE_DIR/ISE_DS/ISE/verilog/src/unisims/DSP48A1.v test_dsp48a1_model_ref.v
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fi
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if [ ! -f "test_dsp48a_model_ref.v" ]; then
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cp $ISE_DIR/ISE_DS/ISE/verilog/src/unisims/DSP48A.v test_dsp48a_model_ref.v
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fi
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for tb in mult_allreg mult_noreg mult_inreg
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do
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iverilog -s $tb -s glbl -o test_dsp48a1_model test_dsp48a1_model.v test_dsp48a1_model_uut.v test_dsp48a1_model_ref.v test_dsp48a_model_ref.v $ISE_DIR/ISE_DS/ISE/verilog/src/glbl.v
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vvp -N ./test_dsp48a1_model
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done
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331
techlibs/xilinx/tests/test_dsp48a1_model.v
Normal file
331
techlibs/xilinx/tests/test_dsp48a1_model.v
Normal file
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@ -0,0 +1,331 @@
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`timescale 1ns / 1ps
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module testbench;
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parameter integer A0REG = 1;
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parameter integer A1REG = 1;
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parameter integer B0REG = 1;
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parameter integer B1REG = 1;
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parameter integer CREG = 1;
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parameter integer DREG = 1;
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parameter integer MREG = 1;
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parameter integer PREG = 1;
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parameter integer CARRYINREG = 1;
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parameter integer CARRYOUTREG = 1;
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parameter integer OPMODEREG = 1;
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parameter CARRYINSEL = "OPMODE5";
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parameter RSTTYPE = "SYNC";
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reg CLK;
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reg CEA, CEB, CEC, CED, CEM, CEP, CECARRYIN, CEOPMODE;
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reg RSTA, RSTB, RSTC, RSTD, RSTM, RSTP, RSTCARRYIN, RSTOPMODE;
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reg [17:0] A;
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reg [17:0] B;
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reg [47:0] C;
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reg [17:0] D;
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reg [47:0] PCIN;
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reg [7:0] OPMODE;
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reg CARRYIN;
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output CARRYOUTF, REF_CARRYOUTF;
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output CARRYOUT, REF_CARRYOUT, REF_OLD_CARRYOUT;
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output [35:0] M, REF_M;
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output [47:0] P, REF_P, REF_OLD_P;
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output [17:0] BCOUT, REF_BCOUT, REF_OLD_BCOUT;
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output [47:0] PCOUT, REF_PCOUT, REF_OLD_PCOUT;
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integer errcount = 0;
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reg ERROR_FLAG = 0;
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task clkcycle;
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begin
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#5;
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CLK = ~CLK;
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#10;
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CLK = ~CLK;
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#2;
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ERROR_FLAG = 0;
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if (REF_BCOUT !== BCOUT || REF_OLD_BCOUT != BCOUT) begin
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$display("ERROR at %1t: REF_BCOUT=%b REF_OLD_BCOUT=%b UUT_BCOUT=%b DIFF=%b", $time, REF_BCOUT, REF_OLD_BCOUT, BCOUT, REF_BCOUT ^ BCOUT);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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if (REF_M !== M) begin
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$display("ERROR at %1t: REF_M=%b UUT_M=%b DIFF=%b", $time, REF_M, M, REF_M ^ M);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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if (REF_P !== P || REF_OLD_P != P) begin
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$display("ERROR at %1t: REF_P=%b REF_OLD_P=%b UUT_P=%b DIFF=%b", $time, REF_P, REF_OLD_P, P, REF_P ^ P);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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if (REF_PCOUT !== PCOUT || REF_OLD_PCOUT != PCOUT) begin
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$display("ERROR at %1t: REF_PCOUT=%b REF_OLD_PCOUT=%b UUT_PCOUT=%b DIFF=%b", $time, REF_PCOUT, REF_OLD_PCOUT, PCOUT, REF_PCOUT ^ PCOUT);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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if (REF_CARRYOUT !== CARRYOUT || (REF_OLD_CARRYOUT != CARRYOUT && !CARRYOUTREG)) begin
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$display("ERROR at %1t: REF_CARRYOUT=%b REF_OLD_CARRYOUT=%b UUT_CARRYOUT=%b DIFF=%b", $time, REF_CARRYOUT, REF_OLD_CARRYOUT, CARRYOUT, REF_CARRYOUT ^ CARRYOUT);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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if (REF_CARRYOUTF !== CARRYOUTF) begin
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$display("ERROR at %1t: REF_CARRYOUTF=%b UUT_CARRYOUTF=%b", $time, REF_CARRYOUTF, CARRYOUTF);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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#3;
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end
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endtask
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reg config_valid = 0;
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task drc;
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begin
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config_valid = 1;
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if (OPMODE[1:0] == 2'b10 && PREG != 1) config_valid = 0;
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if (OPMODE[3:2] == 2'b10 && PREG != 1) config_valid = 0;
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end
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endtask
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initial begin
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$dumpfile("test_dsp48a1_model.vcd");
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$dumpvars(0, testbench);
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#2;
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CLK = 1'b0;
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{CEA, CEB, CEC, CED, CEM, CEP, CECARRYIN, CEOPMODE} = 8'b11111111;
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{A, B, C, D, PCIN, OPMODE, CARRYIN} = 0;
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{RSTA, RSTB, RSTC, RSTD, RSTM, RSTP, RSTCARRYIN, RSTOPMODE} = 8'b11111111;
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repeat (10) begin
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#10;
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CLK = 1'b1;
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#10;
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CLK = 1'b0;
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#10;
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CLK = 1'b1;
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#10;
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CLK = 1'b0;
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end
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{RSTA, RSTB, RSTC, RSTD, RSTM, RSTP, RSTCARRYIN, RSTOPMODE} = 0;
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repeat (10000) begin
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clkcycle;
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config_valid = 0;
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while (!config_valid) begin
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A = $urandom;
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B = $urandom;
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C = {$urandom, $urandom};
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D = $urandom;
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PCIN = {$urandom, $urandom};
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{CEA, CEB, CEC, CED, CEM, CEP, CECARRYIN, CEOPMODE} = $urandom | $urandom | $urandom;
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{RSTA, RSTB, RSTC, RSTD, RSTM, RSTP, RSTCARRYIN, RSTOPMODE} = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom;
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{CARRYIN, OPMODE} = $urandom;
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drc;
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end
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end
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if (errcount == 0) begin
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$display("All tests passed.");
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$finish;
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end else begin
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$display("Caught %1d errors.", errcount);
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$stop;
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end
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end
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DSP48A #(
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.A0REG (A0REG),
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.A1REG (A1REG),
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.B0REG (B0REG),
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.B1REG (B1REG),
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.CREG (CREG),
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.DREG (DREG),
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.MREG (MREG),
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.PREG (PREG),
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.CARRYINREG (CARRYINREG),
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.OPMODEREG (OPMODEREG),
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.CARRYINSEL (CARRYINSEL),
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.RSTTYPE (RSTTYPE)
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) ref_old (
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.A (A),
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.B (B),
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.C (C),
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.D (D),
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.PCIN (PCIN),
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.CARRYIN (CARRYIN),
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.OPMODE (OPMODE),
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.BCOUT (REF_OLD_BCOUT),
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.CARRYOUT (REF_OLD_CARRYOUT),
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.P (REF_OLD_P),
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.PCOUT (REF_OLD_PCOUT),
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.CEA (CEA),
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.CEB (CEB),
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.CEC (CEC),
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.CED (CED),
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.CEM (CEM),
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.CEP (CEP),
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.CECARRYIN (CECARRYIN),
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.CEOPMODE (CEOPMODE),
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.CLK (CLK),
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.RSTA (RSTA),
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.RSTB (RSTB),
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.RSTC (RSTC),
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.RSTD (RSTD),
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.RSTM (RSTM),
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.RSTP (RSTP),
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.RSTCARRYIN (RSTCARRYIN),
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.RSTOPMODE (RSTOPMODE)
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);
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DSP48A1 #(
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.A0REG (A0REG),
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.A1REG (A1REG),
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.B0REG (B0REG),
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.B1REG (B1REG),
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.CREG (CREG),
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.DREG (DREG),
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.MREG (MREG),
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.PREG (PREG),
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.CARRYINREG (CARRYINREG),
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.CARRYOUTREG (CARRYOUTREG),
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.OPMODEREG (OPMODEREG),
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.CARRYINSEL (CARRYINSEL),
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.RSTTYPE (RSTTYPE)
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) ref (
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.A (A),
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.B (B),
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.C (C),
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.D (D),
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.PCIN (PCIN),
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.CARRYIN (CARRYIN),
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.OPMODE (OPMODE),
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.BCOUT (REF_BCOUT),
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.CARRYOUTF (REF_CARRYOUTF),
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.CARRYOUT (REF_CARRYOUT),
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.P (REF_P),
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.M (REF_M),
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.PCOUT (REF_PCOUT),
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.CEA (CEA),
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.CEB (CEB),
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.CEC (CEC),
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.CED (CED),
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.CEM (CEM),
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.CEP (CEP),
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.CECARRYIN (CECARRYIN),
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.CEOPMODE (CEOPMODE),
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.CLK (CLK),
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.RSTA (RSTA),
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.RSTB (RSTB),
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.RSTC (RSTC),
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.RSTD (RSTD),
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.RSTM (RSTM),
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.RSTP (RSTP),
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.RSTCARRYIN (RSTCARRYIN),
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.RSTOPMODE (RSTOPMODE)
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);
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DSP48A1_UUT #(
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.A0REG (A0REG),
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.A1REG (A1REG),
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.B0REG (B0REG),
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.B1REG (B1REG),
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.CREG (CREG),
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.DREG (DREG),
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.MREG (MREG),
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.PREG (PREG),
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.CARRYINREG (CARRYINREG),
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.CARRYOUTREG (CARRYOUTREG),
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.OPMODEREG (OPMODEREG),
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.CARRYINSEL (CARRYINSEL),
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.RSTTYPE (RSTTYPE)
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) uut (
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.A (A),
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.B (B),
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.C (C),
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.D (D),
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.PCIN (PCIN),
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.CARRYIN (CARRYIN),
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.OPMODE (OPMODE),
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.BCOUT (BCOUT),
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.CARRYOUTF (CARRYOUTF),
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.CARRYOUT (CARRYOUT),
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.P (P),
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.M (M),
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.PCOUT (PCOUT),
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.CEA (CEA),
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.CEB (CEB),
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.CEC (CEC),
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.CED (CED),
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.CEM (CEM),
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.CEP (CEP),
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.CECARRYIN (CECARRYIN),
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.CEOPMODE (CEOPMODE),
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.CLK (CLK),
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.RSTA (RSTA),
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.RSTB (RSTB),
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.RSTC (RSTC),
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.RSTD (RSTD),
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.RSTM (RSTM),
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.RSTP (RSTP),
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.RSTCARRYIN (RSTCARRYIN),
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.RSTOPMODE (RSTOPMODE)
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);
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endmodule
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module mult_noreg;
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testbench #(
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.A0REG (0),
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.A1REG (0),
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.B0REG (0),
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.B1REG (0),
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.CREG (0),
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.DREG (0),
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.MREG (0),
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.PREG (0),
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.CARRYINREG (0),
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.CARRYOUTREG (0),
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.OPMODEREG (0),
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.CARRYINSEL ("CARRYIN"),
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.RSTTYPE ("SYNC")
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) testbench ();
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endmodule
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module mult_allreg;
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testbench #(
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.A0REG (1),
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.A1REG (1),
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.B0REG (1),
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.B1REG (1),
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.CREG (1),
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.DREG (1),
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.MREG (1),
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.PREG (1),
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.CARRYINREG (1),
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.CARRYOUTREG (1),
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.OPMODEREG (1),
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.CARRYINSEL ("OPMODE5"),
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.RSTTYPE ("SYNC")
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) testbench ();
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endmodule
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module mult_inreg;
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testbench #(
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.A0REG (1),
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.A1REG (1),
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.B0REG (1),
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.B1REG (1),
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.CREG (1),
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.DREG (1),
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.MREG (0),
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.PREG (0),
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.CARRYINREG (1),
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.CARRYOUTREG (0),
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.OPMODEREG (0),
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.CARRYINSEL ("CARRYIN"),
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.RSTTYPE ("SYNC")
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) testbench ();
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endmodule
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@ -1,14 +1,17 @@
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#!/bin/bash
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set -ex
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if [ -z $VIVADO_DIR ]; then
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VIVADO_DIR=/opt/Xilinx/Vivado/2019.1
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fi
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sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
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if [ ! -f "test_dsp_model_ref.v" ]; then
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cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v
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cp $VIVADO_DIR/data/verilog/src/unisims/DSP48E1.v test_dsp_model_ref.v
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fi
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for tb in macc_overflow_underflow \
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simd24_preadd_noreg_nocasc simd12_preadd_noreg_nocasc \
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mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \
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simd24_preadd_noreg_nocasc simd12_preadd_noreg_nocasc \
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mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \
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mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc mult_inreg_preadd_nocasc
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do
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iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v
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iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v $VIVADO_DIR/data/verilog/src/glbl.v
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vvp -N ./test_dsp_model
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done
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