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Merge pull request #1098 from YosysHQ/xaig

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"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
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Eddie Hung 2019-06-28 10:59:03 -07:00 • committed by GitHub
commit da5f830395
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45 changed files with 3637 additions and 242 deletions
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12
kernel/rtlil.h
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@ -276,6 +276,18 @@ namespace RTLIL
return std::string(c_str() + pos, len);
}
bool begins_with(const char* prefix) const {
size_t len = strlen(prefix);
if (size() < len) return false;
return substr(0, len) == prefix;
}
bool ends_with(const char* suffix) const {
size_t len = strlen(suffix);
if (size() < len) return false;
return substr(size()-len) == suffix;
}
size_t size() const {
return str().size();
}