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Merge pull request #1098 from YosysHQ/xaig

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"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
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Eddie Hung 2019-06-28 10:59:03 -07:00 • committed by GitHub
commit da5f830395
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45 changed files with 3637 additions and 242 deletions
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Makefile
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@ -122,7 +122,7 @@ OBJS = kernel/version_$(GIT_REV).o
# is just a symlink to your actual ABC working directory, as 'make mrproper'
# will remove the 'abc' directory and you do not want to accidentally
# delete your work on ABC..
ABCREV = 3709744
ABCREV = 62487de
ABCPULL = 1
ABCURL ?= https://github.com/berkeley-abc/abc
ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1
@ -688,6 +688,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
+cd tests/opt && bash run-test.sh
+cd tests/aiger && bash run-test.sh $(ABCOPT)
+cd tests/arch && bash run-test.sh
+cd tests/simple_abc9 && bash run-test.sh $(SEEDOPT)
@echo ""
@echo " Passed \"make test\"."
@echo ""