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Create a default selection stack in RTLIL::Design::Design()

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This commit is contained in:
Clifford Wolf 2014-09-02 22:49:24 +02:00
parent c38283dbd0
commit da360771a1
2 changed files with 1 additions and 2 deletions
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2
kernel/yosys.cc
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@ -74,9 +74,7 @@ int SIZE(RTLIL::Wire *wire)
void yosys_setup()
{
Pass::init_register();
yosys_design = new RTLIL::Design;
yosys_design->selection_stack.push_back(RTLIL::Selection());
log_push();
}