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add flag to toggle reg overwriting

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Stan Lee 2026-04-17 15:10:40 -07:00
parent 07ae46f1ea
commit da1072d77d
1 changed files with 11 additions and 2 deletions
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13
passes/sat/sim.cc
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@ -1431,6 +1431,7 @@ struct SimWorker : SimShared
std::string map_filename; std::string map_filename;
std::string summary_filename; std::string summary_filename;
std::string scope; std::string scope;
bool reg_overwrite = false;
~SimWorker() ~SimWorker()
{ {
@ -1736,7 +1737,7 @@ struct SimWorker : SimShared
update(true); update(true);
// Override register state from VCD every cycle // Override register state from VCD every cycle
if (top->setRegisters(time)) if (reg_overwrite && top->setRegisters(time))
update(true); update(true);
register_output_step(time); register_output_step(time);
@ -3097,6 +3098,9 @@ struct SimPass : public Pass {
log(" -log-interval <integer>\n"); log(" -log-interval <integer>\n");
log(" log progress every N cycles (if clock is specified) or samples (otherwise). Defaults to 0 (no logging)\n"); log(" log progress every N cycles (if clock is specified) or samples (otherwise). Defaults to 0 (no logging)\n");
log("\n"); log("\n");
log(" -reg\n");
log(" overwrite register state from VCD file every cycle\n");
log("\n");
} }
@ -3112,7 +3116,7 @@ struct SimPass : public Pass {
int cycle_width = 10; int cycle_width = 10;
int append = 0, log_interval = 0; int append = 0, log_interval = 0;
bool start_set = false, stop_set = false, at_set = false; bool start_set = false, stop_set = false, at_set = false;
bool reg_overwrite = false;
log_header(design, "Executing SIM pass (simulate the circuit).\n"); log_header(design, "Executing SIM pass (simulate the circuit).\n");
size_t argidx; size_t argidx;
@ -3284,6 +3288,10 @@ struct SimPass : public Pass {
worker.outputfiles.emplace_back(std::unique_ptr<AnnotateActivity>(new AnnotateActivity(&worker))); worker.outputfiles.emplace_back(std::unique_ptr<AnnotateActivity>(new AnnotateActivity(&worker)));
continue; continue;
} }
if (args[argidx] == "-reg") {
reg_overwrite = true;
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
@ -3306,6 +3314,7 @@ struct SimPass : public Pass {
top_mod = mods.front(); top_mod = mods.front();
} }
worker.reg_overwrite = reg_overwrite;
if (worker.sim_filename.empty()) if (worker.sim_filename.empty())
worker.run(top_mod, cycle_width, numcycles); worker.run(top_mod, cycle_width, numcycles);
else { else {