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QLF_TDP36K: asymmetric simulation tests

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Krystine Sherwin 2023-12-01 20:47:39 +13:00
parent 0cd4a10c81
commit d9d54e66c7
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tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
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@ -3,6 +3,7 @@ module TB(input clk);
parameter ADDRESS_WIDTH = 10;
parameter DATA_WIDTH = 36;
parameter VECTORLEN = 16;
parameter SHIFT_VAL = 0;
localparam MAX_WIDTH = 36;
reg rce_a_testvector [VECTORLEN-1:0];