mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-11-04 13:29:12 +00:00 
			
		
		
		
	Bugfix in fsm_map for FSMs without reset state
This commit is contained in:
		
							parent
							
								
									aa72262330
								
							
						
					
					
						commit
						d9d38eeedb
					
				
					 1 changed files with 2 additions and 1 deletions
				
			
		| 
						 | 
					@ -272,7 +272,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 | 
				
			||||||
		}
 | 
							}
 | 
				
			||||||
		else
 | 
							else
 | 
				
			||||||
		{
 | 
							{
 | 
				
			||||||
			RTLIL::SigSpec sig_a, sig_b, sig_s;
 | 
								RTLIL::SigSpec sig_a(RTLIL::State::Sx, next_state_wire->width);
 | 
				
			||||||
 | 
								RTLIL::SigSpec sig_b, sig_s;
 | 
				
			||||||
			int reset_state = fsm_data.reset_state;
 | 
								int reset_state = fsm_data.reset_state;
 | 
				
			||||||
			if (reset_state < 0)
 | 
								if (reset_state < 0)
 | 
				
			||||||
				reset_state = 0;
 | 
									reset_state = 0;
 | 
				
			||||||
| 
						 | 
					
 | 
				
			||||||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue