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write_verilog: don't assign to a reg.

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Fixes #2035.
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Catherine 2024-04-03 08:01:58 +00:00 • committed by Marcelina Kościelnicka
parent 040605b047
commit d9a4a42389
4 changed files with 42 additions and 8 deletions
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4
tests/verilog/.gitignore vendored
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@ -1,6 +1,10 @@
/*.log
/*.out
/*.err
/run-test.mk
/const_arst.v
/const_sr.v
/doubleslash.v
/roundtrip_proc_1.v
/roundtrip_proc_2.v
/assign_to_reg.v