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	Fixed memory leak
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		|  | @ -1120,6 +1120,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT | ||||||
| 
 | 
 | ||||||
| 	// Generate RTLIL from AST for the new module and add to the design:
 | 	// Generate RTLIL from AST for the new module and add to the design:
 | ||||||
| 	AstModule *newmod = process_module(new_ast, false); | 	AstModule *newmod = process_module(new_ast, false); | ||||||
|  | 	delete(new_ast); | ||||||
| 	design->add(newmod); | 	design->add(newmod); | ||||||
| 	RTLIL::Module* mod = design->module(original_name); | 	RTLIL::Module* mod = design->module(original_name); | ||||||
| 	if (is_top) | 	if (is_top) | ||||||
|  |  | ||||||
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