mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-09 15:43:25 +00:00
messy
This commit is contained in:
parent
1acbb5b89b
commit
d9943b3727
12 changed files with 1132 additions and 1108 deletions
|
@ -39,6 +39,7 @@ using namespace AST_INTERNAL;
|
|||
// instantiate global variables (public API)
|
||||
namespace AST {
|
||||
std::string current_filename;
|
||||
bool sv_mode;
|
||||
unsigned long long astnodes = 0;
|
||||
unsigned long long astnode_count() { return astnodes; }
|
||||
}
|
||||
|
@ -1402,6 +1403,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
|
|||
log_assert(current_ast->type == AST_DESIGN);
|
||||
for (const auto& child : current_ast->children)
|
||||
{
|
||||
child->dumpAst(stdout, "child: ");
|
||||
if (child->type == AST_MODULE || child->type == AST_INTERFACE)
|
||||
{
|
||||
for (auto& n : design->verilog_globals)
|
||||
|
@ -1459,6 +1461,10 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
|
|||
|
||||
process_module(design, child.get(), defer_local);
|
||||
current_ast_mod = nullptr;
|
||||
log("built this:\n");
|
||||
log_module(design->module(child->str));
|
||||
log("here:\n");
|
||||
Pass::call(design, "dump");
|
||||
}
|
||||
else if (child->type == AST_PACKAGE) {
|
||||
// process enum/other declarations
|
||||
|
@ -1480,6 +1486,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
|
|||
current_scope.clear();
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
// An interface port with modport is specified like this:
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue