From 7a9d727bd0319619b3d1a37bd5998977ef0c3ac9 Mon Sep 17 00:00:00 2001 From: Gary Wong Date: Thu, 29 May 2025 21:26:28 -0600 Subject: [PATCH] docs: several small documentation fixes. --- docs/source/appendix/primer.rst | 8 ++++---- .../more_scripting/interactive_investigation.rst | 2 +- docs/source/using_yosys/synthesis/abc.rst | 2 +- docs/source/yosys_internals/flow/verilog_frontend.rst | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/docs/source/appendix/primer.rst b/docs/source/appendix/primer.rst index 50656af78..f54f99e52 100644 --- a/docs/source/appendix/primer.rst +++ b/docs/source/appendix/primer.rst @@ -72,7 +72,7 @@ circuits. Tools exist to synthesize high level code (usually in the form of C/C++/SystemC code with additional metadata) to behavioural HDL code (usually in the form of Verilog or VHDL code). Aside from the many commercial tools for high level -synthesis there are also a number of FOSS tools for high level synthesis . +synthesis there are also a number of FOSS tools for high level synthesis. Behavioural level ~~~~~~~~~~~~~~~~~ @@ -185,7 +185,7 @@ advantage that it has a unique normalized form. The latter has much better worst case performance and is therefore better suited for the synthesis of large logic functions. -Good FOSS tools exists for multi-level logic synthesis . +Good FOSS tools exists for multi-level logic synthesis. Yosys contains basic logic synthesis functionality but can also use ABC for the logic synthesis step. Using ABC is recommended. @@ -221,7 +221,7 @@ design description as input and generates an RTL, logical gate or physical gate level description of the design as output. Yosys' main strengths are behavioural and RTL synthesis. A wide range of commands (synthesis passes) exist within Yosys that can be used to perform a wide range of synthesis tasks within the -domain of behavioural, rtl and logic synthesis. Yosys is designed to be +domain of behavioural, RTL and logic synthesis. Yosys is designed to be extensible and therefore is a good basis for implementing custom synthesis tools for specialised tasks. @@ -572,7 +572,7 @@ of lexical tokens given in :numref:`Tab. %s `. TOK_SEMICOLON \- ============== =============== -The lexer is usually generated by a lexer generator (e.g. flex ) from a +The lexer is usually generated by a lexer generator (e.g. flex) from a description file that is using regular expressions to specify the text pattern that should match the individual tokens. diff --git a/docs/source/using_yosys/more_scripting/interactive_investigation.rst b/docs/source/using_yosys/more_scripting/interactive_investigation.rst index c6180306d..e9c9bc9ac 100644 --- a/docs/source/using_yosys/more_scripting/interactive_investigation.rst +++ b/docs/source/using_yosys/more_scripting/interactive_investigation.rst @@ -73,7 +73,7 @@ contain bits that are not 0 or 1 (i.e. ``x`` or ``z``). Ordinary 32-bit constants are written using decimal numbers. Single-bit signals are shown as thin arrows pointing from the driver to the -load. Signals that are multiple bits wide are shown as think arrows. +load. Signals that are multiple bits wide are shown as thick arrows. Finally *processes* are shown in boxes with round corners. Processes are Yosys' internal representation of the decision-trees and synchronization events diff --git a/docs/source/using_yosys/synthesis/abc.rst b/docs/source/using_yosys/synthesis/abc.rst index 91de775e6..0b24af3a1 100644 --- a/docs/source/using_yosys/synthesis/abc.rst +++ b/docs/source/using_yosys/synthesis/abc.rst @@ -176,5 +176,5 @@ implemented as whiteboxes too. Boxes are arguably the biggest advantage that ABC9 has over ABC: by being aware of carry chains and DSPs, it avoids optimising for a path that isn't the actual critical path, while the generally-longer paths result in ABC9 being able to -reduce design area by mapping other logic to larger-but-slower cells. +reduce design area by mapping other logic to smaller-but-slower cells. diff --git a/docs/source/yosys_internals/flow/verilog_frontend.rst b/docs/source/yosys_internals/flow/verilog_frontend.rst index e53466687..b6a7ba8a0 100644 --- a/docs/source/yosys_internals/flow/verilog_frontend.rst +++ b/docs/source/yosys_internals/flow/verilog_frontend.rst @@ -626,7 +626,7 @@ pass and the passes it launches: | This pass replaces the ``RTLIL::SyncRule``\ s to d-type flip-flops (with asynchronous resets if necessary). -- | `proc_dff` +- | `proc_memwr` | This pass replaces the ``RTLIL::MemWriteAction``\ s with `$memwr` cells. - | `proc_clean`