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Fix all comments from PR

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SergeyDegtyar 2019-08-21 21:52:07 +03:00
parent b835ec37cb
commit d945b8a357
20 changed files with 465 additions and 160 deletions
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tests/ice40/mul.ys Normal file
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read_verilog mul.v
hierarchy -top top
synth -flatten -run coarse # technology-independent coarse grained synthesis
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check same as technology-dependent fine-grained synthesis
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 15 t:SB_LUT4
select -assert-count 3 t:SB_CARRY
select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D