mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Added missing fixup_ports() calls to "rename" command

Browse source
This commit is contained in:
Clifford Wolf 2014-11-08 12:38:48 +01:00
parent 003336c58d
commit d92fb5b35e
1 changed files with 4 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/cmds/rename.cc
View file

@ -36,6 +36,8 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
if (it.first == from_name) {
log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
module->rename(it.second, to_name);
if (it.second->port_id)
module->fixup_ports();
return;
}
@ -124,6 +126,7 @@ struct RenamePass : public Pass {
new_wires[it.second->name] = it.second;
}
module->wires_.swap(new_wires);
module->fixup_ports();
std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
for (auto &it : module->cells_) {
@ -154,6 +157,7 @@ struct RenamePass : public Pass {
new_wires[it.second->name] = it.second;
}
module->wires_.swap(new_wires);
module->fixup_ports();
std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
for (auto &it : module->cells_) {