mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-12-09 21:33:26 +00:00
Code Activity

Added ranged case check

Browse source
This commit is contained in:
Miodrag Milanovic 2023-02-23 15:04:31 +01:00
parent 53a4f0fb56
commit d8cefec169
2 changed files with 27 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

11
tests/verific/range_case.sv Normal file
View file

@ -0,0 +1,11 @@
module top(input clk, input signed [3:0] sel_w , output reg out);
always @ (posedge clk)
begin
case (sel_w) inside
[-4:3] : out <= 1'b1;
[4:5] : out <= 1'b0;
endcase
end
endmodule