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Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro

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This commit is contained in:
Eddie Hung 2019-08-19 09:56:17 -07:00
parent 5abe133323
commit d81a090d89
4 changed files with 12 additions and 12 deletions
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4
techlibs/ice40/cells_sim.v
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@ -143,11 +143,11 @@ endmodule
(* abc_box_id = 1, lib_whitebox *)
module \$__ICE40_FULL_ADDER (
(* abc_carry_out *) output CO,
(* abc_carry *) output CO,
output O,
input A,
input B,
(* abc_carry_in *) input CI
(* abc_carry *) input CI
);
SB_CARRY carry (
.I0(A),