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https://github.com/YosysHQ/yosys
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Merge pull request #3185 from YosysHQ/micko/co_sim
Add co-simulation in sim pass
This commit is contained in:
Miodrag Milanović
GitHub
commit
d7f7227ce8
20 changed files with 11555 additions and 23 deletions
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@ -21,12 +21,49 @@
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/mem.h"
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#include "kernel/fstdata.h"
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#include <ctime>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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enum class SimulationMode {
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sim,
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cmp,
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gold,
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gate,
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};
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static const std::map<std::string, int> g_units =
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{
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{ "", -9 }, // default is ns
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{ "s", 0 },
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{ "ms", -3 },
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{ "us", -6 },
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{ "ns", -9 },
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{ "ps", -12 },
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{ "fs", -15 },
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{ "as", -18 },
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{ "zs", -21 },
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};
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static double stringToTime(std::string str)
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{
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if (str=="END") return -1;
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char *endptr;
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long value = strtol(str.c_str(), &endptr, 10);
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if (g_units.find(endptr)==g_units.end())
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log_error("Cannot parse '%s', bad unit '%s'\n", str.c_str(), endptr);
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if (value < 0)
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log_error("Time value '%s' must be positive\n", str.c_str());
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return value * pow(10.0, g_units.at(endptr));
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}
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struct SimShared
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{
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bool debug = false;
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@ -34,6 +71,11 @@ struct SimShared
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bool writeback = false;
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bool zinit = false;
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int rstlen = 1;
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FstData *fst = nullptr;
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double start_time = 0;
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double stop_time = -1;
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SimulationMode sim_mode = SimulationMode::sim;
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bool cycles_set = false;
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};
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void zinit(State &v)
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@ -51,7 +93,8 @@ void zinit(Const &v)
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struct SimInstance
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{
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SimShared *shared;
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std::string scope;
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Module *module;
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Cell *instance;
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@ -92,9 +135,11 @@ struct SimInstance
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std::vector<Mem> memories;
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dict<Wire*, pair<int, Const>> vcd_database;
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dict<Wire*, pair<fstHandle, Const>> fst_database;
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dict<Wire*, fstHandle> fst_handles;
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SimInstance(SimShared *shared, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
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shared(shared), module(module), instance(instance), parent(parent), sigmap(module)
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SimInstance(SimShared *shared, std::string scope, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
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shared(shared), scope(scope), module(module), instance(instance), parent(parent), sigmap(module)
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{
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log_assert(module);
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@ -116,6 +161,13 @@ struct SimInstance
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}
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}
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if ((shared->fst) && !(shared->hide_internal && wire->name[0] == '$')) {
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fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
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if (id==0 && wire->name.isPublic())
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log_warning("Unable to found wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name)).c_str());
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fst_handles[wire] = id;
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}
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if (wire->attributes.count(ID::init)) {
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Const initval = wire->attributes.at(ID::init);
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for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++)
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@ -144,7 +196,7 @@ struct SimInstance
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Module *mod = module->design->module(cell->type);
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if (mod != nullptr) {
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dirty_children.insert(new SimInstance(shared, mod, cell, this));
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dirty_children.insert(new SimInstance(shared, scope + "." + RTLIL::unescape_id(cell->name), mod, cell, this));
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}
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for (auto &port : cell->connections()) {
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@ -622,14 +674,125 @@ struct SimInstance
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for (auto child : children)
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child.second->write_vcd_step(f);
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}
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void write_fst_header(struct fstContext *f)
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{
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fstWriterSetScope(f, FST_ST_VCD_MODULE, stringf("%s",log_id(name())).c_str(), nullptr);
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for (auto wire : module->wires())
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{
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if (shared->hide_internal && wire->name[0] == '$')
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continue;
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fstHandle id = fstWriterCreateVar(f, FST_VT_VCD_WIRE, FST_VD_IMPLICIT, GetSize(wire),
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stringf("%s%s", wire->name[0] == '$' ? "\\" : "", log_id(wire)).c_str(), 0);
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fst_database[wire] = make_pair(id, Const());
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}
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for (auto child : children)
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child.second->write_fst_header(f);
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fstWriterSetUpscope(f);
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}
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void write_fst_step(struct fstContext *f)
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{
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for (auto &it : fst_database)
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{
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Wire *wire = it.first;
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Const value = get_state(wire);
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fstHandle id = it.second.first;
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if (it.second.second == value)
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continue;
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it.second.second = value;
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std::stringstream ss;
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for (int i = GetSize(value)-1; i >= 0; i--) {
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switch (value[i]) {
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case State::S0: ss << "0"; break;
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case State::S1: ss << "1"; break;
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case State::Sx: ss << "x"; break;
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default: ss << "z";
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}
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}
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fstWriterEmitValueChange(f, id, ss.str().c_str());
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}
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for (auto child : children)
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child.second->write_fst_step(f);
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}
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void setInitState(uint64_t time)
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{
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for (auto &it : ff_database)
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{
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Cell *cell = it.first;
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SigSpec qsig = cell->getPort(ID::Q);
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if (qsig.is_wire()) {
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IdString name = qsig.as_wire()->name;
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fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(name));
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if (id==0 && name.isPublic())
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log_warning("Unable to found wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(name)).c_str());
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if (id!=0) {
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Const fst_val = Const::from_string(shared->fst->valueAt(id, time));
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set_state(qsig, fst_val);
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}
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}
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}
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for (auto child : children)
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child.second->setInitState(time);
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}
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bool checkSignals(uint64_t time)
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{
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bool retVal = false;
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for(auto &item : fst_handles) {
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if (item.second==0) continue; // Ignore signals not found
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Const fst_val = Const::from_string(shared->fst->valueAt(item.second, time));
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Const sim_val = get_state(item.first);
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if (sim_val.size()!=fst_val.size())
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log_error("Signal '%s' size is different in gold and gate.\n", log_id(item.first));
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if (shared->sim_mode == SimulationMode::sim) {
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// No checks performed when using stimulus
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} else if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
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for(int i=0;i<fst_val.size();i++) {
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if (fst_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
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log_warning("Signal '%s' in file %s in simulation %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
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retVal = true;
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break;
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}
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}
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} else if (shared->sim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X
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for(int i=0;i<sim_val.size();i++) {
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if (sim_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
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log_warning("Signal '%s' in file %s in simulation %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
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retVal = true;
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break;
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}
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}
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} else {
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if (fst_val!=sim_val) {
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log_warning("Signal '%s' in file %s in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
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retVal = true;
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}
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}
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}
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for (auto child : children)
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retVal |= child.second->checkSignals(time);
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return retVal;
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}
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};
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struct SimWorker : SimShared
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{
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SimInstance *top = nullptr;
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std::ofstream vcdfile;
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struct fstContext *fstfile = nullptr;
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pool<IdString> clock, clockn, reset, resetn;
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std::string timescale;
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std::string sim_filename;
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std::string scope;
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~SimWorker()
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{
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@ -638,9 +801,6 @@ struct SimWorker : SimShared
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void write_vcd_header()
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{
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if (!vcdfile.is_open())
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return;
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vcdfile << stringf("$version %s $end\n", yosys_version_str);
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std::time_t t = std::time(nullptr);
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@ -660,13 +820,53 @@ struct SimWorker : SimShared
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void write_vcd_step(int t)
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{
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if (!vcdfile.is_open())
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return;
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vcdfile << stringf("#%d\n", t);
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top->write_vcd_step(vcdfile);
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}
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void write_fst_header()
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{
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std::time_t t = std::time(nullptr);
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fstWriterSetDate(fstfile, asctime(std::localtime(&t)));
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fstWriterSetVersion(fstfile, yosys_version_str);
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if (!timescale.empty())
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fstWriterSetTimescaleFromString(fstfile, timescale.c_str());
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fstWriterSetPackType(fstfile, FST_WR_PT_FASTLZ);
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fstWriterSetRepackOnClose(fstfile, 1);
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top->write_fst_header(fstfile);
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}
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void write_fst_step(int t)
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{
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fstWriterEmitTimeChange(fstfile, t);
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top->write_fst_step(fstfile);
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}
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void write_output_header()
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{
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if (vcdfile.is_open())
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write_vcd_header();
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if (fstfile)
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write_fst_header();
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}
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void write_output_step(int t)
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{
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if (vcdfile.is_open())
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write_vcd_step(t);
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if (fstfile)
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write_fst_step(t);
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}
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void write_output_end()
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{
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if (fstfile)
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fstWriterClose(fstfile);
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}
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void update()
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{
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while (1)
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@ -705,7 +905,7 @@ struct SimWorker : SimShared
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void run(Module *topmod, int numcycles)
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{
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log_assert(top == nullptr);
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top = new SimInstance(this, topmod);
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top = new SimInstance(this, scope, topmod);
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if (debug)
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log("\n===== 0 =====\n");
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@ -720,24 +920,25 @@ struct SimWorker : SimShared
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update();
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write_vcd_header();
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write_vcd_step(0);
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write_output_header();
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write_output_step(0);
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for (int cycle = 0; cycle < numcycles; cycle++)
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{
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if (debug)
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log("\n===== %d =====\n", 10*cycle + 5);
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else
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log("Simulating cycle %d.\n", (cycle*2)+1);
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set_inports(clock, State::S0);
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set_inports(clockn, State::S1);
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update();
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write_vcd_step(10*cycle + 5);
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write_output_step(10*cycle + 5);
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if (debug)
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log("\n===== %d =====\n", 10*cycle + 10);
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else
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log("Simulating cycle %d.\n", cycle+1);
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log("Simulating cycle %d.\n", (cycle*2)+2);
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set_inports(clock, State::S1);
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set_inports(clockn, State::S0);
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@ -748,11 +949,132 @@ struct SimWorker : SimShared
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}
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update();
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write_vcd_step(10*cycle + 10);
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write_output_step(10*cycle + 10);
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}
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write_vcd_step(10*numcycles + 2);
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write_output_step(10*numcycles + 2);
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write_output_end();
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if (writeback) {
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pool<Module*> wbmods;
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top->writeback(wbmods);
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}
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}
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void run_cosim(Module *topmod, int numcycles)
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{
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log_assert(top == nullptr);
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fst = new FstData(sim_filename);
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if (scope.empty())
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log_error("Scope must be defined for co-simulation.\n");
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top = new SimInstance(this, scope, topmod);
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std::vector<fstHandle> fst_clock;
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for (auto portname : clock)
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{
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Wire *w = topmod->wire(portname);
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if (!w)
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log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
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if (!w->port_input)
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log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
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fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
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if (id==0)
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log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
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fst_clock.push_back(id);
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}
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for (auto portname : clockn)
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{
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Wire *w = topmod->wire(portname);
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if (!w)
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log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
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if (!w->port_input)
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log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
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fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
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if (id==0)
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log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
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fst_clock.push_back(id);
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}
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if (fst_clock.size()==0)
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log_error("No clock signals defined for input file\n");
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SigMap sigmap(topmod);
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std::map<Wire*,fstHandle> inputs;
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for (auto wire : topmod->wires()) {
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if (wire->port_input) {
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fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
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if (id==0)
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log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str());
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inputs[wire] = id;
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}
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}
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uint64_t startCount = 0;
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uint64_t stopCount = 0;
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if (start_time==0) {
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if (start_time < fst->getStartTime())
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log_warning("Start time is before simulation file start time\n");
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startCount = fst->getStartTime();
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} else if (start_time==-1)
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startCount = fst->getEndTime();
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else {
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startCount = start_time / fst->getTimescale();
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if (startCount > fst->getEndTime()) {
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startCount = fst->getEndTime();
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log_warning("Start time is after simulation file end time\n");
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}
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}
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if (stop_time==0) {
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if (stop_time < fst->getStartTime())
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log_warning("Stop time is before simulation file start time\n");
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stopCount = fst->getStartTime();
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} else if (stop_time==-1)
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stopCount = fst->getEndTime();
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else {
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stopCount = stop_time / fst->getTimescale();
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if (stopCount > fst->getEndTime()) {
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stopCount = fst->getEndTime();
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log_warning("Stop time is after simulation file end time\n");
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}
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}
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if (stopCount<startCount) {
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log_error("Stop time is before start time\n");
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}
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auto samples = fst->getAllEdges(fst_clock, startCount, stopCount);
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// Limit to number of cycles if provided
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if (cycles_set && ((size_t)(numcycles *2) < samples.size()))
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samples.erase(samples.begin() + (numcycles*2), samples.end());
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// Add setup time (start time)
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if (samples.empty() || samples.front()!=startCount)
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samples.insert(samples.begin(), startCount);
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fst->reconstructAllAtTimes(samples);
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bool initial = true;
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int cycle = 0;
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log("Co-simulation from %lu%s to %lu%s\n", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
|
||||
for(auto &time : samples) {
|
||||
log("Co-simulating cycle %d [%lu%s].\n", cycle, (unsigned long)time, fst->getTimescaleString());
|
||||
for(auto &item : inputs) {
|
||||
std::string v = fst->valueAt(item.second, time);
|
||||
top->set_state(item.first, Const::from_string(v));
|
||||
}
|
||||
if (initial) {
|
||||
top->setInitState(time);
|
||||
initial = false;
|
||||
}
|
||||
update();
|
||||
|
||||
bool status = top->checkSignals(time);
|
||||
if (status)
|
||||
log_error("Signal difference\n");
|
||||
cycle++;
|
||||
}
|
||||
if (writeback) {
|
||||
pool<Module*> wbmods;
|
||||
top->writeback(wbmods);
|
||||
|
|
@ -773,6 +1095,9 @@ struct SimPass : public Pass {
|
|||
log(" -vcd <filename>\n");
|
||||
log(" write the simulation results to the given VCD file\n");
|
||||
log("\n");
|
||||
log(" -fst <filename>\n");
|
||||
log(" write the simulation results to the given FST file\n");
|
||||
log("\n");
|
||||
log(" -clock <portname>\n");
|
||||
log(" name of top-level clock input\n");
|
||||
log("\n");
|
||||
|
|
@ -795,14 +1120,41 @@ struct SimPass : public Pass {
|
|||
log(" include the specified timescale declaration in the vcd\n");
|
||||
log("\n");
|
||||
log(" -n <integer>\n");
|
||||
log(" number of cycles to simulate (default: 20)\n");
|
||||
log(" number of clock cycles to simulate (default: 20)\n");
|
||||
log("\n");
|
||||
log(" -a\n");
|
||||
log(" include all nets in VCD output, not just those with public names\n");
|
||||
log(" use all nets in VCD/FST operations, not just those with public names\n");
|
||||
log("\n");
|
||||
log(" -w\n");
|
||||
log(" writeback mode: use final simulation state as new init state\n");
|
||||
log("\n");
|
||||
log(" -r\n");
|
||||
log(" read simulation results file (file formats supported: FST)\n");
|
||||
log("\n");
|
||||
log(" -scope\n");
|
||||
log(" scope of simulation top model\n");
|
||||
log("\n");
|
||||
log(" -at <time>\n");
|
||||
log(" sets start and stop time\n");
|
||||
log("\n");
|
||||
log(" -start <time>\n");
|
||||
log(" start co-simulation in arbitary time (default 0)\n");
|
||||
log("\n");
|
||||
log(" -stop <time>\n");
|
||||
log(" stop co-simulation in arbitary time (default END)\n");
|
||||
log("\n");
|
||||
log(" -sim\n");
|
||||
log(" simulation with stimulus from FST (default)\n");
|
||||
log("\n");
|
||||
log(" -sim-cmp\n");
|
||||
log(" co-simulation expect exact match\n");
|
||||
log("\n");
|
||||
log(" -sim-gold\n");
|
||||
log(" co-simulation, x in simulation can match any value in FST\n");
|
||||
log("\n");
|
||||
log(" -sim-gate\n");
|
||||
log(" co-simulation, x in FST can match any value in simulation\n");
|
||||
log("\n");
|
||||
log(" -d\n");
|
||||
log(" enable debug output\n");
|
||||
log("\n");
|
||||
|
|
@ -811,6 +1163,7 @@ struct SimPass : public Pass {
|
|||
{
|
||||
SimWorker worker;
|
||||
int numcycles = 20;
|
||||
bool start_set = false, stop_set = false, at_set = false;
|
||||
|
||||
log_header(design, "Executing SIM pass (simulate the circuit).\n");
|
||||
|
||||
|
|
@ -822,8 +1175,15 @@ struct SimPass : public Pass {
|
|||
worker.vcdfile.open(vcd_filename.c_str());
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-fst" && argidx+1 < args.size()) {
|
||||
std::string fst_filename = args[++argidx];
|
||||
rewrite_filename(fst_filename);
|
||||
worker.fstfile = (struct fstContext *)fstWriterCreate(fst_filename.c_str(),1);
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-n" && argidx+1 < args.size()) {
|
||||
numcycles = atoi(args[++argidx].c_str());
|
||||
worker.cycles_set = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-rstlen" && argidx+1 < args.size()) {
|
||||
|
|
@ -866,9 +1226,55 @@ struct SimPass : public Pass {
|
|||
worker.zinit = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-r" && argidx+1 < args.size()) {
|
||||
std::string sim_filename = args[++argidx];
|
||||
rewrite_filename(sim_filename);
|
||||
worker.sim_filename = sim_filename;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-scope" && argidx+1 < args.size()) {
|
||||
worker.scope = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-start" && argidx+1 < args.size()) {
|
||||
worker.start_time = stringToTime(args[++argidx]);
|
||||
start_set = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-stop" && argidx+1 < args.size()) {
|
||||
worker.stop_time = stringToTime(args[++argidx]);
|
||||
stop_set = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-at" && argidx+1 < args.size()) {
|
||||
worker.start_time = stringToTime(args[++argidx]);
|
||||
worker.stop_time = worker.start_time;
|
||||
at_set = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-sim") {
|
||||
worker.sim_mode = SimulationMode::sim;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-sim-cmp") {
|
||||
worker.sim_mode = SimulationMode::cmp;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-sim-gold") {
|
||||
worker.sim_mode = SimulationMode::gold;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-sim-gate") {
|
||||
worker.sim_mode = SimulationMode::gate;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
if (at_set && (start_set || stop_set || worker.cycles_set))
|
||||
log_error("'at' option can only be defined separate of 'start','stop' and 'n'\n");
|
||||
if (stop_set && worker.cycles_set)
|
||||
log_error("'stop' and 'n' can only be used exclusively'\n");
|
||||
|
||||
Module *top_mod = nullptr;
|
||||
|
||||
|
|
@ -884,7 +1290,10 @@ struct SimPass : public Pass {
|
|||
top_mod = mods.front();
|
||||
}
|
||||
|
||||
worker.run(top_mod, numcycles);
|
||||
if (worker.sim_filename.empty())
|
||||
worker.run(top_mod, numcycles);
|
||||
else
|
||||
worker.run_cosim(top_mod, numcycles);
|
||||
}
|
||||
} SimPass;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue