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Convert to use #945

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This commit is contained in:
Eddie Hung 2019-04-21 15:19:02 -07:00
parent 42a6e0b0b9
commit d7f0700bae
2 changed files with 3 additions and 9 deletions
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10
techlibs/ice40/cells_sim.v
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@ -127,20 +127,14 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
assign O = I0 ? s1[1] : s1[0]; assign O = I0 ? s1[1] : s1[0];
endmodule endmodule
(* abc_box_id = 21 *) (* abc_box_id = 21, lib_whitebox *)
`ifdef ABC_MODEL
(* whitebox *)
`endif
module SB_CARRY (output CO, input I0, I1, CI); module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI); assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule endmodule
// Positive Edge SiliconBlue FF Cells // Positive Edge SiliconBlue FF Cells
(* abc_box_id = 1, abc_flop *) (* abc_box_id = 1, abc_flop, lib_whitebox *)
`ifdef ABC_MODEL
(* whitebox *)
`endif
module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D); module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
`ifndef ABC_MODEL `ifndef ABC_MODEL
always @(posedge C) always @(posedge C)

2
techlibs/ice40/synth_ice40.cc
View file

@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
{ {
if (check_label("begin")) if (check_label("begin"))
{ {
run("read_verilog -wb -D ABC_MODEL +/ice40/cells_sim.v"); run("read_verilog -lib -D ABC_MODEL +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run("proc"); run("proc");
} }