mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-06 19:21:23 +00:00
Code Activity

Convert to use #945

Browse source
This commit is contained in:
Eddie Hung 2019-04-21 15:19:02 -07:00
parent 42a6e0b0b9
commit d7f0700bae
2 changed files with 3 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

10
techlibs/ice40/cells_sim.v
View file

@ -127,20 +127,14 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
assign O = I0 ? s1[1] : s1[0];
endmodule
(* abc_box_id = 21 *)
`ifdef ABC_MODEL
(* whitebox *)
`endif
(* abc_box_id = 21, lib_whitebox *)
module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule
// Positive Edge SiliconBlue FF Cells
(* abc_box_id = 1, abc_flop *)
`ifdef ABC_MODEL
(* whitebox *)
`endif
(* abc_box_id = 1, abc_flop, lib_whitebox *)
module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
`ifndef ABC_MODEL
always @(posedge C)