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[core] add rf techlibs
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26
techlibs/rapidflex/src/rf_dsp_mad.pmg
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26
techlibs/rapidflex/src/rf_dsp_mad.pmg
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@ -0,0 +1,26 @@
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pattern rf_dsp_mad
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state <IdString> add_ba
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state <int> mul_nusers
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state <int> add_nusers
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match mul
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select mul->type.in($mul)
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select nusers(port(mul, \Y)) <= 3
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set mul_nusers nusers(port(mul, \Y))
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endmatch
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match add
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select add->type.in($add, $sub)
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choice <IdString> AB {\A, \B}
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define <IdString> BA (AB == \A ? \B : \A)
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index <SigSpec> port(add, AB) === port(mul, \Y)
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select nusers(port(add, \Y)) <= 3
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set add_nusers nusers(port(add, \Y))
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set add_ba BA
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endmatch
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code
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accept;
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endcode
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