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[core] add rf techlibs

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tangxifan 2026-05-14 17:33:24 -07:00
parent 54f8505045
commit d7cf53d86a
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15
techlibs/rapidflex/alkaidL/cell_sim_arith.v Normal file
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//---------------------------------------
// 1-bit adder
//---------------------------------------
(* abc9_box, lib_whitebox *)
module _fpga_adder(
output sumout,
output cout,
input a,
input b,
input cin
);
assign sumout = a ^ b ^ cin;
assign cout = (a & b) | ((a | b) & cin);
endmodule