mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-01 04:58:54 +00:00
Code Activity

[core] add rf techlibs

Browse source
This commit is contained in:
tangxifan 2026-05-14 17:33:24 -07:00
parent 54f8505045
commit d7cf53d86a
49 changed files with 34443 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

154
techlibs/rapidflex/alkaidC/arith_map.v Normal file
View file

@ -0,0 +1,154 @@
// Arithmetic units: adder
// Adapt from: https://github.com/chipsalliance/yosys-f4pga-plugins/blob/0ad1af26a29243a9e76379943d735e119dcd0cc6/ql-qlf-plugin/qlf_k6n10/cells_sim.v
// Many thanks to F4PGA for their contribution
(* techmap_celltype = "$alu" *)
module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH-1:0] CO;
// The max. number of adders we can support in AlkaidS is (12x2-1)x4x16 = 1472
// Fail when resource limit exceeds
// Also fail when a low utilization rate is detected
// Originally prefer to defer carry mapping when < 2-bit adder is detected
// Due to a bug found in scalable seq detector, the bound is increased to 4-bit adder
wire _TECHMAP_FAIL_ = Y_WIDTH > 1472 || Y_WIDTH < 4;
generate
if ((A_WIDTH == 0 || B_WIDTH == 0) && Y_WIDTH > 0) begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";
localparam Y_COL_WIDTH = 96 - 3;
localparam Y_MAX_WIDTH = 12 - 3;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH: 0] CARRY;
assign CO[Y_WIDTH-1:0] = CARRY[Y_WIDTH:1];
genvar i;
generate if (Y_WIDTH < Y_COL_WIDTH) begin
wire CARRY_end_buf;
wire [1024:0] _TECHMAP_DO_ = "insbuf CARRY[Y_WIDTH] CARRY_end_buf";
_fpga_adder intermediate_adder (
.cin ( ),
.cout (CARRY[0]),
.a (CI ),
.b (CI ),
.sumout ( )
);
_fpga_adder first_adder (
.cin (CARRY[0]),
.cout (CARRY[1]),
.a (AA[0] ),
.b (BB[0] ),
.sumout (Y[0] )
);
_fpga_adder pretaill_adder (
.cin (CARRY[Y_WIDTH-1] ),
.cout (CARRY_end_buf),
.a (AA[Y_WIDTH-1] ),
.b (BB[Y_WIDTH-1] ),
.sumout (Y[Y_WIDTH-1] )
);
_fpga_adder tail_adder (
.cin (CARRY_end_buf),
.cout (),
.a (1'b0),
.b (1'b0),
.sumout (CARRY[Y_WIDTH])
);
generate for (i = 1; i < Y_WIDTH-1 ; i = i+1) begin:gen3
_fpga_adder my_adder (
.cin (CARRY[i] ),
.cout (CARRY[i+1]),
.a (AA[i] ),
.b (BB[i] ),
.sumout (Y[i] )
);
end endgenerate
end else begin
generate for (i = 0; i < Y_WIDTH ; i = i+1) begin:gen4
// Due to VPR limitations regarding IO connexion to carry chain,
// we generate the carry chain input signal using an intermediate adder
// since we can connect a & b from io pads, but not cin & cout
if (i == 0) begin
_fpga_adder intermediate_adder (
.cin ( ),
.cout (CARRY[0]),
.a (CI ),
.b (CI ),
.sumout ( )
);
_fpga_adder first_adder (
.cin (CARRY[0]),
.cout (CARRY[1]),
.a (AA[0] ),
.b (BB[0] ),
.sumout (Y[0] )
);
end else if (i % (Y_MAX_WIDTH + 1) == 0) begin
wire CARRY_end_buf;
wire CARRY_start_buf;
wire [1024:0] _TECHMAP_DO_ = "insbuf CARRY[i+1] CARRY_end_buf; insbuf CARRY_end_buf CARRY_start_buf";
_fpga_adder tail_adder (
.cin (CARRY[i]),
.cout (),
.a (1'b0),
.b (1'b0),
.sumout (CARRY_end_buf)
);
_fpga_adder intermediate_adder (
.cin ( ),
.cout (CARRY_start_buf),
.a (CARRY_end_buf),
.b (1'b1),
.sumout ( )
);
_fpga_adder first_adder (
.cin (CARRY_start_buf),
.cout (CARRY[i+1]),
.a (AA[i] ),
.b (BB[i] ),
.sumout (Y[i] )
);
end else begin
_fpga_adder my_adder (
.cin (CARRY[i] ),
.cout (CARRY[i+1]),
.a (AA[i] ),
.b (BB[i] ),
.sumout (Y[i] )
);
end
end endgenerate
end endgenerate
assign X = AA ^ BB;
endmodule

29
techlibs/rapidflex/alkaidC/ccb_inst_code.v Normal file
View file

@ -0,0 +1,29 @@
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// File name: define.v
// Descriptions: This file is the opcode for ccb tile instructions
// Author: Yihong
// Date: 2025/8/14
// Revision: 0.0.1
// Revision History:
// V0.0.1 - 2025/8/14 initial release
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Operations
`define ADD 4'b1000
`define SUB 4'b1001
`define PUSH 4'b1010
`define PULL 4'b1011
`define MOV 4'b1100
`define MOV_T1 4'b1101
`define MOV_T2 4'b1110
`define INTR 4'b1111
`define NA 10'h000
// SRC/DES
`define R0 3'b000
`define R1 3'b001
`define R2 3'b010
`define R3 3'b011
`define C0 3'b100
`define C1 3'b101
`define C2 3'b110

8
techlibs/rapidflex/alkaidC/cell_sim.v Normal file
View file

@ -0,0 +1,8 @@
//-------------------------------------------------
// Include all the primitives
//-------------------------------------------------
`include "cell_sim_arith.v"
`include "cell_sim_ff.v"
`include "cell_sim_pcnt.v"
`include "ccb_inst_code.v"
`include "cell_sim_ccb.v"

15
techlibs/rapidflex/alkaidC/cell_sim_arith.v Normal file
View file

@ -0,0 +1,15 @@
//---------------------------------------
// 1-bit adder
//---------------------------------------
(* abc9_box, lib_whitebox *)
module _fpga_adder(
output sumout,
output cout,
input a,
input b,
input cin
);
assign sumout = a ^ b ^ cin;
assign cout = (a & b) | ((a | b) & cin);
endmodule

101
techlibs/rapidflex/alkaidC/cell_sim_ccb.v Normal file
View file

@ -0,0 +1,101 @@
//-------------------------------------------------
// Counter Configuration Block (CCB) Primitives
//-------------------------------------------------
`default_nettype none
module ccb # (
// Location constraints
parameter FPGA_LOC_X = 0,
parameter FPGA_LOC_Y = 0,
parameter FPGA_LOC_Z = 0,
// Event0 triggered instructions
parameter [0:9] EVENT0_INST0 = `NA,
parameter [0:9] EVENT0_INST1 = `NA,
parameter [0:9] EVENT0_INST2 = `NA,
parameter [0:9] EVENT0_INST3 = `NA,
parameter [0:9] EVENT0_INST4 = `NA,
parameter [0:9] EVENT0_INST5 = `NA,
parameter [0:9] EVENT0_INST6 = `NA,
parameter [0:9] EVENT0_INST7 = `NA,
// Event1 triggered instructions
parameter [0:9] EVENT1_INST0 = `NA,
parameter [0:9] EVENT1_INST1 = `NA,
parameter [0:9] EVENT1_INST2 = `NA,
parameter [0:9] EVENT1_INST3 = `NA,
parameter [0:9] EVENT1_INST4 = `NA,
parameter [0:9] EVENT1_INST5 = `NA,
parameter [0:9] EVENT1_INST6 = `NA,
parameter [0:9] EVENT1_INST7 = `NA,
// Event2 triggered instructions
parameter [0:9] EVENT2_INST0 = `NA,
parameter [0:9] EVENT2_INST1 = `NA,
parameter [0:9] EVENT2_INST2 = `NA,
parameter [0:9] EVENT2_INST3 = `NA,
parameter [0:9] EVENT2_INST4 = `NA,
parameter [0:9] EVENT2_INST5 = `NA,
parameter [0:9] EVENT2_INST6 = `NA,
parameter [0:9] EVENT2_INST7 = `NA,
// Event3 triggered instructions
parameter [0:9] EVENT3_INST0 = `NA,
parameter [0:9] EVENT3_INST1 = `NA,
parameter [0:9] EVENT3_INST2 = `NA,
parameter [0:9] EVENT3_INST3 = `NA,
parameter [0:9] EVENT3_INST4 = `NA,
parameter [0:9] EVENT3_INST5 = `NA,
parameter [0:9] EVENT3_INST6 = `NA,
parameter [0:9] EVENT3_INST7 = `NA,
// Initial register values, R0-R3
parameter [0:31] R0 = {32{1'b0}},
parameter [0:31] R1 = {32{1'b0}},
parameter [0:31] R2 = {32{1'b0}},
parameter [0:31] R3 = {32{1'b0}},
// FIFO initial values
parameter [0:31] FIFO_INIT0 = {32{1'b0}},
parameter [0:31] FIFO_INIT1 = {32{1'b0}},
parameter [0:31] FIFO_INIT2 = {32{1'b0}},
parameter [0:31] FIFO_INIT3 = {32{1'b0}},
// PCNT initial values
parameter [0:31] LOAD_VAL_PCNT0 = {32{1'b0}},
parameter [0:31] LOAD_VAL_PCNT1 = {32{1'b0}},
parameter [0:31] LOAD_VAL_PCNT2 = {32{1'b0}},
parameter [0:31] MATCH0_REF_PCNT0 = {32{1'b0}},
parameter [0:31] MATCH0_REF_PCNT1 = {32{1'b0}},
parameter [0:31] MATCH0_REF_PCNT2 = {32{1'b0}},
parameter [0:31] MATCH1_REF_PCNT0 = {32{1'b0}},
parameter [0:31] MATCH1_REF_PCNT1 = {32{1'b0}},
parameter [0:31] MATCH1_REF_PCNT2 = {32{1'b0}}
)(
input ccb_clk_i,
input ccb_rst_ni,
input [0:3] ccb_event_i,
input [0:5] pcnt_event_i,
output [0:31] match0_ref0_o,
output [0:31] match1_ref0_o,
output [0:31] load_val0_o,
output [0:31] match0_ref1_o,
output [0:31] match1_ref1_o,
output [0:31] load_val1_o,
output [0:31] match0_ref2_o,
output [0:31] match1_ref2_o,
output [0:31] load_val2_o
);
// Dummy
assign match0_ref0_o = 0;
assign match1_ref0_o = 0;
assign load_val0_o = 0;
assign match0_ref1_o = 0;
assign match1_ref1_o = 0;
assign load_val1_o = 0;
assign match0_ref2_o = 0;
assign match1_ref2_o = 0;
assign load_val2_o = 0;
endmodule
`default_nettype wire

586
techlibs/rapidflex/alkaidC/cell_sim_ff.v Normal file
View file

@ -0,0 +1,586 @@
//-----------------------------
// Rising-edge D-type flip-flop
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dff(
output reg Q,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C)
Q <= D;
1'b1:
always @(negedge C)
Q <= D;
endcase
endmodule
//-----------------------------
// Rising-edge D-type flip-flop with active-high asynchronous reset
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffr(
output reg Q,
input D,
input R,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or posedge R)
if (R == 1'b1)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C or posedge R)
if (R == 1'b1)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule
//-----------------------------
// Rising-edge D-type flip-flop with active-high asynchronous set
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffs(
output reg Q,
input D,
input S,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or posedge S)
if (S == 1'b1)
Q <= 1'b1;
else
Q <= D;
1'b1:
always @(negedge C or posedge S)
if (S == 1'b1)
Q <= 1'b1;
else
Q <= D;
endcase
endmodule
//-----------------------------
// Rising-edge D-type flip-flop with active-low asynchronous reset
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffrn(
output reg Q,
input D,
input RN,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or negedge RN)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C or negedge RN)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule
//-----------------------------
// Rising-edge D-type flip-flop with active-low asynchronous set
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffsn(
output reg Q,
input D,
input SN,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or negedge SN)
if (SN == 1'b0)
Q <= 1'b1;
else
Q <= D;
1'b1:
always @(negedge C or negedge SN)
if (SN == 1'b0)
Q <= 1'b1;
else
Q <= D;
endcase
endmodule
//-----------------------------
// Rising-edge D-type flip-flop with active-high synchronous reset
//-----------------------------
(* abc9_flop, lib_whitebox *)
module sdffr(
output reg Q,
input D,
input R,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C)
if (R == 1'b1)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C)
if (R == 1'b1)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule
//-----------------------------
// Rising-edge D-type flip-flop with active-high synchronous set
//-----------------------------
(* abc9_flop, lib_whitebox *)
module sdffs(
output reg Q,
input D,
input S,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C)
if (S == 1'b1)
Q <= 1'b1;
else
Q <= D;
1'b1:
always @(negedge C)
if (S == 1'b1)
Q <= 1'b1;
else
Q <= D;
endcase
endmodule
//-----------------------------
// Rising-edge D-type flip-flop with active-low synchronous reset
//-----------------------------
(* abc9_flop, lib_whitebox *)
module sdffrn(
output reg Q,
input D,
input RN,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule
//-----------------------------
// Rising-edge D-type flip-flop with active-low synchronous set
//-----------------------------
(* abc9_flop, lib_whitebox *)
module sdffsn(
output reg Q,
input D,
input SN,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C)
if (SN == 1'b0)
Q <= 1'b1;
else
Q <= D;
1'b1:
always @(negedge C)
if (SN == 1'b0)
Q <= 1'b1;
else
Q <= D;
endcase
endmodule
//-----------------------------
// Falling-edge D-type flip-flop
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffn(
output reg Q,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b1;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C)
Q <= D;
1'b1:
always @(negedge C)
Q <= D;
endcase
endmodule
//-----------------------------
// Falling-edge D-type flip-flop with active-high asynchronous reset
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffnr(
output reg Q,
input D,
input R,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b1;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or posedge R)
if (R == 1'b1)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C or posedge R)
if (R == 1'b1)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule
//-----------------------------
// Falling-edge D-type flip-flop with active-high asynchronous set
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffns(
output reg Q,
input D,
input S,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b1;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or posedge S)
if (S == 1'b1)
Q <= 1'b1;
else
Q <= D;
1'b1:
always @(negedge C or posedge S)
if (S == 1'b1)
Q <= 1'b1;
else
Q <= D;
endcase
endmodule
//-----------------------------
// Falling-edge D-type flip-flop with active-low asynchronous reset
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffnrn(
output reg Q,
input D,
input RN,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b1;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or negedge RN)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C or negedge RN)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule
//-----------------------------
// Falling-edge D-type flip-flop with active-low asynchronous set
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffnsn(
output reg Q,
input D,
input SN,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b1;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or negedge SN)
if (SN == 1'b0)
Q <= 1'b1;
else
Q <= D;
1'b1:
always @(negedge C or negedge SN)
if (SN == 1'b0)
Q <= 1'b1;
else
Q <= D;
endcase
endmodule
//-----------------------------
// Falling-edge D-type flip-flop with active-high synchronous reset
//-----------------------------
(* abc9_flop, lib_whitebox *)
module sdffnr(
output reg Q,
input D,
input R,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b1;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C)
if (R == 1'b1)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C)
if (R == 1'b1)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule
//-----------------------------
// Falling-edge D-type flip-flop with active-high synchronous set
//-----------------------------
(* abc9_flop, lib_whitebox *)
module sdffns(
output reg Q,
input D,
input S,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b1;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C)
if (S == 1'b1)
Q <= 1'b1;
else
Q <= D;
1'b1:
always @(negedge C)
if (S == 1'b1)
Q <= 1'b1;
else
Q <= D;
endcase
endmodule
//-----------------------------
// Falling-edge D-type flip-flop with active-low synchronous reset
//-----------------------------
(* abc9_flop, lib_whitebox *)
module sdffnrn(
output reg Q,
input D,
input RN,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b1;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule
//-----------------------------
// Falling-edge D-type flip-flop with active-low synchronous set
//-----------------------------
(* abc9_flop, lib_whitebox *)
module sdffnsn(
output reg Q,
input D,
input SN,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b1;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C)
if (SN == 1'b0)
Q <= 1'b1;
else
Q <= D;
1'b1:
always @(negedge C)
if (SN == 1'b0)
Q <= 1'b1;
else
Q <= D;
endcase
endmodule
//-----------------------------
// Two-bit D-type flip-flop with active-high asynchronous reset
// 1st stage is positive-edge triggered
// 2nd stage is negative-edge triggered
//-----------------------------
// Do not allow ABC or other optimization to touch the ff!
//(* abc9_flop, lib_whitebox *)
module dffnr_dffr(
output Q,
input D,
input R,
input C
);
wire Q0;
dffnr FF_0 (.D(D), .C(C), .R(R), .Q(Q0));
dffr FF_1 (.D(Q0), .C(C), .R(R), .Q(Q));
endmodule
//-----------------------------
// Two-bit D-type flip-flop with active-high asynchronous reset
// 1st stage is positive-edge triggered
// 2nd stage is negative-edge triggered
//-----------------------------
// Do not allow ABC or other optimization to touch the ff!
//(* abc9_flop, lib_whitebox *)
module dffr_dffnr(
output Q,
input D,
input R,
input C
);
wire Q0;
dffr FF_0 (.D(D), .C(C), .R(R), .Q(Q0));
dffnr FF_1 (.D(Q0), .C(C), .R(R), .Q(Q));
endmodule

9691
techlibs/rapidflex/alkaidC/cell_sim_pcnt.v Normal file
View file

File diff suppressed because it is too large Load diff

177
techlibs/rapidflex/alkaidC/dff_map.v Normal file
View file

@ -0,0 +1,177 @@
// Rising edge DFF
module \$_DFF_P_ (D, C, Q);
input D;
input C;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
endmodule
// Rising edge DFF with async active-high reset
module \$_DFF_PP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
// Rising edge DFF with async active-high set
module \$_DFF_PP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
endmodule
// Rising edge DFF with async active-low reset
module \$_DFF_PN0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
endmodule
// Rising edge DFF with async active-low set
module \$_DFF_PN1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R));
endmodule
// Rising edge DFF with sync active-high reset
module \$_SDFF_PP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
sdffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
// Rising edge DFF with sync active-high set
module \$_SDFF_PP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
sdffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
endmodule
// Rising edge DFF with sync active-low reset
module \$_SDFF_PN0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
sdffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
endmodule
// Rising edge DFF with sync active-low set
module \$_SDFF_PN1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
sdffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R));
endmodule
// Falling edge DFF
module \$_DFF_N_ (D, C, Q);
input D;
input C;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
endmodule
// Falling edge DFF with async active-high reset
module \$_DFF_NP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffnr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
// Falling edge DFF with async active-high set
module \$_DFF_NP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffns _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
endmodule
// Falling edge DFF with async active-low reset
module \$_DFF_NN0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffnrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
endmodule
// Falling edge DFF with async active-low set
module \$_DFF_NN1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffnsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R));
endmodule
// Falling edge DFF with sync active-high reset
module \$_SDFF_NP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
sdffnr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
// Falling edge DFF with sync active-high set
module \$_SDFF_NP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
sdffns _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
endmodule
// Falling edge DFF with sync active-low reset
module \$_SDFF_NN0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
sdffnrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
endmodule
// Falling edge DFF with sync active-low set
module \$_SDFF_NN1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
sdffnsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R));
endmodule

128
techlibs/rapidflex/alkaidC/synth.ys Normal file
View file

@ -0,0 +1,128 @@
# Yosys synthesis script for ${TOP_MODULE}
#########################
# Parse input files
#########################
# Read verilog files
read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
# Read technology library
read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
#########################
# Prepare for synthesis
#########################
# Identify top module from hierarchy
hierarchy -check -top ${TOP_MODULE}
# - Convert process blocks to AST
proc
# Flatten all the gates/primitives
flatten
# Identify tri-state buffers from 'z' signal in AST
# with follow-up optimizations to clean up AST
tribuf -logic
opt_expr
opt_clean
# demote inout ports to input or output port
# with follow-up optimizations to clean up AST
deminout
opt -nodffe
opt_expr
opt_clean
check
opt -nodffe
wreduce -keepdc
peepopt
pmuxtree
opt_clean
########################
# Map multipliers
# Inspired from synth_xilinx.cc
#########################
# Avoid merging any registers into DSP, reserve memory port registers first
#memory_dff
#wreduce t:$mul
#techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS}
#select a:mul2dsp
#setattr -unset mul2dsp
#opt_expr -fine
#wreduce
#select -clear
#chtype -set $mul t:$__soft_mul# Extract arithmetic functions
#########################
# Run coarse synthesis
#########################
# Run a tech map with default library
alumacc
#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG}
#opt -fast -nodffe
#opt_expr
#opt_merge
#opt_clean
#opt -nodffe
#share
#opt -nodffe
#fsm
# Run a quick follow-up optimization to sweep out unused nets/signals
#opt -fast -nodffe
opt
# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells
memory -nomap
opt_clean
#########################
# Map logics to BRAMs
#########################
#memory_bram -rules ${YOSYS_BRAM_MAP_RULES}
#techmap -map ${YOSYS_BRAM_MAP_VERILOG}
#opt -fast -mux_undef -undriven -fine -nodffe
#memory_map
#opt -undriven -fine -nodffe
########################
# Map Adders
techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG}
opt -fast -nodffe
opt_expr
opt_merge
opt_clean
opt -nodffe
#########################
# Map flip-flops
#########################
memory
dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01
techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG}
dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01
techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG}
opt_expr -mux_undef
simplemap
opt_expr
opt_merge
opt_dff -nodffe
opt_clean
opt -nodffe
#########################
# Map LUTs
#########################
abc -lut ${LUT_SIZE}
# Map dff again since ABC may generate some new FFs
techmap -map ${YOSYS_DFF_MAP_VERILOG}
techmap -map ${YOSYS_ADDER_MAP_VERILOG}
#########################
# Check and show statisitics
#########################
hierarchy -check
stat
#########################
# Output netlists
#########################
opt_clean -purge
write_blif ${OUTPUT_BLIF}
write_verilog ${TOP_MODULE}_post_synth.v

128
techlibs/rapidflex/alkaidC/synth_no_adder.ys Normal file
View file

@ -0,0 +1,128 @@
# Yosys synthesis script for ${TOP_MODULE}
#########################
# Parse input files
#########################
# Read verilog files
read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
# Read technology library
read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
#########################
# Prepare for synthesis
#########################
# Identify top module from hierarchy
hierarchy -check -top ${TOP_MODULE}
# - Convert process blocks to AST
proc
# Flatten all the gates/primitives
flatten
# Identify tri-state buffers from 'z' signal in AST
# with follow-up optimizations to clean up AST
tribuf -logic
opt_expr
opt_clean
# demote inout ports to input or output port
# with follow-up optimizations to clean up AST
deminout
opt -nodffe
opt_expr
opt_clean
check
opt -nodffe
wreduce -keepdc
peepopt
pmuxtree
opt_clean
########################
# Map multipliers
# Inspired from synth_xilinx.cc
#########################
# Avoid merging any registers into DSP, reserve memory port registers first
#memory_dff
#wreduce t:$mul
#techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS}
#select a:mul2dsp
#setattr -unset mul2dsp
#opt_expr -fine
#wreduce
#select -clear
#chtype -set $mul t:$__soft_mul# Extract arithmetic functions
#########################
# Run coarse synthesis
#########################
# Run a tech map with default library
alumacc
#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG}
#opt -fast -nodffe
#opt_expr
#opt_merge
#opt_clean
#opt -nodffe
#share
#opt -nodffe
#fsm
# Run a quick follow-up optimization to sweep out unused nets/signals
#opt -fast -nodffe
opt
# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells
memory -nomap
opt_clean
#########################
# Map logics to BRAMs
#########################
#memory_bram -rules ${YOSYS_BRAM_MAP_RULES}
#techmap -map ${YOSYS_BRAM_MAP_VERILOG}
#opt -fast -mux_undef -undriven -fine -nodffe
#memory_map
#opt -undriven -fine -nodffe
########################
# Map Adders
#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG}
#opt -fast -nodffe
#opt_expr
#opt_merge
#opt_clean
#opt -nodffe
#########################
# Map flip-flops
#########################
memory
dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01
techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG}
dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01
techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG}
opt_expr -mux_undef
simplemap
opt_expr
opt_merge
opt_dff -nodffe
opt_clean
opt -nodffe
#########################
# Map LUTs
#########################
abc -lut ${LUT_SIZE}
# Map dff again since ABC may generate some new FFs
techmap -map ${YOSYS_DFF_MAP_VERILOG}
techmap -map ${YOSYS_ADDER_MAP_VERILOG}
#########################
# Check and show statisitics
#########################
hierarchy -check
stat
#########################
# Output netlists
#########################
opt_clean -purge
write_blif ${OUTPUT_BLIF}
write_verilog ${TOP_MODULE}_post_synth.v

41
techlibs/rapidflex/alkaidC/verilog_rewrite.ys Normal file
View file

@ -0,0 +1,41 @@
# Yosys synthesis script for ${TOP_MODULE}
# Read verilog files
read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
# Technology mapping
hierarchy -top ${TOP_MODULE}
proc
techmap -D NO_LUT -map +/adff2dff.v
# Synthesis
flatten
opt_expr
opt_clean
check
opt -nodffe -nosdff
fsm
opt -nodffe -nosdff
wreduce
peepopt
opt_clean
opt -nodffe -nosdff
memory -nomap
opt_clean
opt -fast -full -nodffe -nosdff
memory_map
opt -full -nodffe -nosdff
techmap
opt -fast -nodffe -nosdff
clean
clean
# LUT mapping
abc -lut ${LUT_SIZE}
# Check
synth -run check
# Clean and output blif
opt_clean -purge
write_verilog ${OUTPUT_VERILOG}