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https://github.com/YosysHQ/yosys
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Merge 2eb1051cca into 09f9e0e8d1
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nataliakokoromyti
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commit
d7b71e2597
4 changed files with 307 additions and 0 deletions
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@ -24,6 +24,7 @@ OBJS += passes/opt/opt_ffinv.o
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OBJS += passes/opt/pmux2shiftx.o
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OBJS += passes/opt/muxpack.o
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OBJS += passes/opt/splitlarge.o
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OBJS += passes/opt/peepopt.o
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GENFILES += passes/opt/peepopt_pm.h
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passes/opt/peepopt.o: passes/opt/peepopt_pm.h
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201
passes/opt/splitlarge.cc
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201
passes/opt/splitlarge.cc
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@ -0,0 +1,201 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* 2025 Silimate Inc. <akash@silimate.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/utils.h"
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#include <queue>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SplitlargeWorker
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{
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Module *module;
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int max_width;
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SplitlargeWorker(Module *module, int max_width) : module(module), max_width(max_width)
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{
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}
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void split_spec(int high_width, int low_width, SigSpec &high, SigSpec &low, const SigSpec &splittable, bool sign_extend)
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{
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SigSpec splittable_ext = splittable;
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splittable_ext.extend_u0(high_width + low_width, sign_extend);
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high = splittable_ext.extract(low_width, high_width);
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low = splittable_ext.extract(0, low_width);
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}
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int width_addsub(Cell *cell)
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{
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int a_width = cell->parameters[ID::A_WIDTH].as_int();
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int b_width = cell->parameters[ID::B_WIDTH].as_int();
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return max(a_width, b_width);
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}
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void split_addsub(Cell *cell, std::queue<Cell *>& q)
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{
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auto width = width_addsub(cell);
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auto width_low = width / 2;
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auto width_high = width - width_low; // Handle odd widths
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bool aSigned = cell->parameters[ID::A_SIGNED].as_bool();
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bool bSigned = cell->parameters[ID::B_SIGNED].as_bool();
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SigSpec aHigh, aLow, bHigh, bLow;
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split_spec(width_high, width_low, aHigh, aLow, cell->getPort(ID::A), cell->getParam(ID::A_SIGNED).as_bool());
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split_spec(width_high, width_low, bHigh, bLow, cell->getPort(ID::B), cell->getParam(ID::B_SIGNED).as_bool());
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std::string yHighName = cell->name.str() + "_splitres1";
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std::string yCarryName = cell->name.str() + "_splitresc";
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std::string yLowName = cell->name.str() + "_splitres0";
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std::string nameHigh = cell->name.str() + "_split1";
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std::string nameLow = cell->name.str() + "_split0";
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std::string nameCarry = cell->name.str() + "_splitc";
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auto yCarry = module->addWire(yCarryName, width_high + 1);
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auto yHigh = module->addWire(yHighName, width_high + 1);
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auto yLow = module->addWire(yLowName, width_low + 1);
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auto backupResultSpec = cell->getPort(ID::Y);
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// Modify existing adder to be low
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module->rename(cell, nameLow);
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cell->setPort(ID::A, aLow);
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cell->setPort(ID::B, bLow);
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cell->setPort(ID::Y, yLow);
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cell->parameters[ID::A_WIDTH] = width_low;
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cell->parameters[ID::B_WIDTH] = width_low;
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cell->parameters[ID::Y_WIDTH] = width_low + 1;
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cell->parameters[ID::A_SIGNED] = 0;
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cell->parameters[ID::B_SIGNED] = 0;
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if (width_low > max_width) {
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q.emplace(cell);
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}
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// Create high adder
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auto highCell = module->addCell(nameHigh, cell); // copy type and parameters
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highCell->setPort(ID::A, aHigh);
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highCell->setPort(ID::B, bHigh);
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highCell->setPort(ID::Y, yHigh);
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highCell->parameters[ID::A_WIDTH] = width_high;
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highCell->parameters[ID::B_WIDTH] = width_high;
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highCell->parameters[ID::Y_WIDTH] = width_high + 1;
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highCell->parameters[ID::A_SIGNED] = aSigned;
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highCell->parameters[ID::B_SIGNED] = bSigned;
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if (width_high > max_width) {
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q.emplace(highCell);
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}
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// Create carry adder
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auto carryCell = module->addCell(nameCarry, highCell); // copy type and parameters
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auto carryBit = SigSpec(yLow).extract(width_low, 1);
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carryBit.extend_u0(2);
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carryCell->setPort(ID::A, yHigh);
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carryCell->parameters[ID::A_WIDTH] = width_high + 1;
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carryCell->parameters[ID::A_SIGNED] = aSigned || bSigned;
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carryCell->setPort(ID::B, carryBit);
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carryCell->parameters[ID::B_WIDTH] = 2;
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carryCell->parameters[ID::B_SIGNED] = aSigned || bSigned;
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carryCell->setPort(ID::Y, yCarry);
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if (width_high + 1 > max_width) {
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q.emplace(carryCell);
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}
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// Concatenate
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auto ySpec = SigSpec({yCarry, SigSpec(yLow).extract(0, width_low)});
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module->connect(backupResultSpec, ySpec.extract(0, backupResultSpec.size()));
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}
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void split()
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{
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std::queue<Cell *> q;
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for (auto pair: module->cells_) {
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auto& cell = pair.second;
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if (cell->type == ID($add) && width_addsub(cell) > max_width) {
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q.emplace(cell);
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} else if (cell->type == ID($sub) && width_addsub(cell) > max_width) {
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q.emplace(cell);
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}
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}
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while (!q.empty()) {
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auto cell = q.front();
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q.pop();
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if (cell->type == ID($add)) {
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split_addsub(cell, q);
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}
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else if (cell->type == ID($sub)) {
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split_addsub(cell, q);
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}
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}
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}
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};
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struct SplitlargePass : public Pass {
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SplitlargePass() : Pass("splitlarge", "splitting large arithmetic operators") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" splitlarge [selection]\n");
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log("\n");
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log(" splits arithmetic operators (specifically $add, $sub) into a number of\n");
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log(" operators with smaller widths. should be run after techmap/simplemap\n");
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log("\n");
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log("\n");
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log(" -max_width n\n");
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log(" max tolerable width of an $add or $sub operator.\n");
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log(" * The width of $add/$sub is defined as max(a_width, b_width)\n");
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log(" * If unset, 128 is used as a default value.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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int max_width = 128;
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log_header(design, "Executing SPLITLARGE pass (splitting wide $add/$sub operators).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-max_width" && argidx+1 < args.size()) {
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max_width = std::stoul(args[++argidx]);
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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SplitlargeWorker worker(module, max_width);
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worker.split();
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}
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Pass::call(design, "clean *");
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}
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} SplitlargePass;
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PRIVATE_NAMESPACE_END
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71
tests/opt/splitlarge_wide_op.tcl
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71
tests/opt/splitlarge_wide_op.tcl
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@ -0,0 +1,71 @@
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proc op_name {op_number} {
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set op [expr $op_number >> 2]
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set b_signed [expr {$op_number & 1 ? "signed": "unsigned"}]
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set a_signed [expr {(($op_number & 2) >> 1) ? "signed": "unsigned"}]
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set cell "unknown"
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if { "$op" == "0" } {
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set cell "\$add"
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} elseif { "$op" == "1" } {
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set cell "\$sub"
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}
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return "$cell (a $a_signed, b $b_signed)"
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}
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proc predict_adder_count {in_width max_width op_number} {
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set b_signed [expr {$op_number & 1}]
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set a_signed [expr {($op_number & 2) >> 1}]
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set a_width [expr {$in_width + $a_signed}]
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set b_width [expr {$in_width + $b_signed}]
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set adder_width [expr {max($a_width, $b_width)}]
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set adder_queue [list]
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if {$adder_width > $max_width} {
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lappend adder_queue $adder_width
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}
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set adder_count 1
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while {[llength $adder_queue] > 0} {
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set current [lindex $adder_queue end]
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set adder_queue [lrange $adder_queue 0 end-1]
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incr adder_count 2 ; # one changed adder, two new adders
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set low [expr {$current / 2}]
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set high [expr {$current - $low}]
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set carry [expr {$high + 1}]
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if {$low > $max_width} {
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lappend adder_queue $low
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}
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if {$high > $max_width} {
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lappend adder_queue $high
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}
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if {$carry > $max_width} {
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lappend adder_queue $carry
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}
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}
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return $adder_count
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}
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yosys -import
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log -header "splitlarge"
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log -push
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for {set i 0} {$i < 8} {incr i} {
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log -header "[op_name $i]"
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log -push
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design -reset
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read_verilog splitlarge_wide_op.v
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hierarchy -top wide_op
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chparam -set width 1024 -set op $i wide_op
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yosys proc
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simplemap
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equiv_opt -assert splitlarge
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yosys splitlarge
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yosys select -assert-none r:A_WIDTH>128
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yosys select -assert-none r:B_WIDTH>128
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yosys select -assert-count [predict_adder_count 1024 128 $i] r:A_WIDTH
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log -pop
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}
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log -pop
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34
tests/opt/splitlarge_wide_op.v
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34
tests/opt/splitlarge_wide_op.v
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@ -0,0 +1,34 @@
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module wide_op(
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a, b, y, c
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);
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parameter width = 1024;
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// ADD/SUB: 0/4 + (0 unsigned;unsigned, 1 unsigned;signed, 2 signed;unsigned, 3 signed;signed)
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parameter op = 0;
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localparam ywidth = width; // (op == MUL) ? width * 2 : width;
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input[width-1:0] a;
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input[width-1:0] b;
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output [width-1:0] y;
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output c;
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generate
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if (op == 0)
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assign {c, y} = a + b;
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else if (op == 1)
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assign {c, y} = a + $signed(b);
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else if (op == 2)
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assign {c, y} = $signed(a) + b;
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else if (op == 3)
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assign {c, y} = $signed(a) + $signed(b);
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else if (op == 4)
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assign {c, y} = a - b;
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else if (op == 5)
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assign {c, y} = a - $signed(b);
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else if (op == 6)
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assign {c, y} = $signed(a) - b;
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else if (op == 7)
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assign {c, y} = $signed(a) - $signed(b);
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endgenerate
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endmodule
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