Merge pull request #3903 from jix/dft-future_ff

Basic support for tag primitives and `$future_ff`

frontends/verific/verific.cc

@@ -74,7 +74,7 @@ USING_YOSYS_NAMESPACE
 #  error "Only YosysHQ flavored Verific is supported. Please contact office@yosyshq.com for commercial support for Yosys+Verific."
 #endif
 
-#if YOSYSHQ_VERIFIC_API_VERSION < 20210801
+#if YOSYSHQ_VERIFIC_API_VERSION < 20230901
 #  error "Please update your version of YosysHQ flavored Verific."
 #endif
 
@@ -251,6 +251,14 @@ static const RTLIL::Const verific_const(const char *value, bool allow_string = t
 	return c;
 }
 
+static const std::string verific_unescape(const char *value)
+{
+	std::string val = std::string(value);
+	if (val.size()>1 && val[0]=='\"' && val.back()=='\"')
+		return val.substr(1,val.size()-2);
+	return value;
+}
+
 void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj, Netlist *nl)
 {
 	MapIter mi;
@@ -1103,6 +1111,43 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 		return true;
 	}
 
+	if (inst->Type() == OPER_YOSYSHQ_SET_TAG)
+	{
+		RTLIL::SigSpec sig_expr = operatorInport(inst, "expr");
+		RTLIL::SigSpec sig_set_mask = operatorInport(inst, "set_mask");
+		RTLIL::SigSpec sig_clr_mask = operatorInport(inst, "clr_mask");
+		RTLIL::SigSpec sig_o = operatorOutput(inst);
+		std::string tag = inst->GetAtt("tag") ? verific_unescape(inst->GetAttValue("tag")) : "";
+		module->connect(sig_o, module->SetTag(new_verific_id(inst), tag, sig_expr, sig_set_mask, sig_clr_mask));
+		return true;
+	}
+	if (inst->Type() == OPER_YOSYSHQ_GET_TAG)
+	{
+		std::string tag = inst->GetAtt("tag") ? verific_unescape(inst->GetAttValue("tag")) : "";
+		module->connect(operatorOutput(inst),module->GetTag(new_verific_id(inst), tag, operatorInput(inst)));
+		return true;
+	}
+	if (inst->Type() == OPER_YOSYSHQ_OVERWRITE_TAG)
+	{
+		RTLIL::SigSpec sig_signal = operatorInport(inst, "signal");
+		RTLIL::SigSpec sig_set_mask = operatorInport(inst, "set_mask");
+		RTLIL::SigSpec sig_clr_mask = operatorInport(inst, "clr_mask");
+		std::string tag = inst->GetAtt("tag") ? verific_unescape(inst->GetAttValue("tag")) : "";
+		module->addOverwriteTag(new_verific_id(inst), tag, sig_signal, sig_set_mask, sig_clr_mask);
+		return true;
+	}
+	if (inst->Type() == OPER_YOSYSHQ_ORIGINAL_TAG)
+	{
+		std::string tag = inst->GetAtt("tag") ? verific_unescape(inst->GetAttValue("tag")) : "";
+		module->connect(operatorOutput(inst),module->OriginalTag(new_verific_id(inst), tag, operatorInput(inst)));
+		return true;
+	}
+	if (inst->Type() == OPER_YOSYSHQ_FUTURE_FF)
+	{
+		module->connect(operatorOutput(inst),module->FutureFF(new_verific_id(inst), operatorInput(inst)));
+		return true;
+	}
+
 	#undef IN
 	#undef IN1
 	#undef IN2

kernel/celltypes.h

@@ -102,6 +102,11 @@ struct CellTypes
 		setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);
 		setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
 		setup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
+		setup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});
+		setup_type(ID($get_tag), {ID::A}, {ID::Y});
+		setup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool<RTLIL::IdString>());
+		setup_type(ID($original_tag), {ID::A}, {ID::Y});
+		setup_type(ID($future_ff), {ID::A}, {ID::Y});
 	}
 
 	void setup_internals_eval()

kernel/constids.inc

@@ -208,6 +208,7 @@ X(syn_romstyle)
 X(S_WIDTH)
 X(T)
 X(TABLE)
+X(TAG)
 X(techmap_autopurge)
 X(_TECHMAP_BITS_CONNMAP_)
 X(_TECHMAP_CELLNAME_)

kernel/rtlil.cc

@@ -1828,6 +1828,40 @@ namespace {
 					ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_)))
 				{ port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
 
+			if (cell->type.in(ID($set_tag))) {
+				param(ID::WIDTH);
+				param(ID::TAG);
+				port(ID::A, param(ID::WIDTH));
+				port(ID::SET, param(ID::WIDTH));
+				port(ID::CLR, param(ID::WIDTH));
+				port(ID::Y, param(ID::WIDTH));
+				check_expected();
+				return;
+			}
+			if (cell->type.in(ID($get_tag),ID($original_tag))) {
+				param(ID::WIDTH);
+				param(ID::TAG);
+				port(ID::A, param(ID::WIDTH));
+				port(ID::Y, param(ID::WIDTH));
+				check_expected();
+				return;
+			}
+			if (cell->type.in(ID($overwrite_tag))) {
+				param(ID::WIDTH);
+				param(ID::TAG);
+				port(ID::A, param(ID::WIDTH));
+				port(ID::SET, param(ID::WIDTH));
+				port(ID::CLR, param(ID::WIDTH));
+				check_expected();
+				return;
+			}
+			if (cell->type.in(ID($future_ff))) {
+				param(ID::WIDTH);
+				port(ID::A, param(ID::WIDTH));
+				port(ID::Y, param(ID::WIDTH));
+				check_expected();
+				return;
+			}
 			error(__LINE__);
 		}
 	};
@@ -3246,6 +3280,80 @@ RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string
 	return sig;
 }
 
+RTLIL::SigSpec RTLIL::Module::SetTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src)
+{
+	RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size());
+	Cell *cell = addCell(name, ID($set_tag));
+	cell->parameters[ID::WIDTH] = sig_a.size();
+	cell->parameters[ID::TAG] = tag;
+	cell->setPort(ID::A, sig_a);
+	cell->setPort(ID::SET, sig_s);
+	cell->setPort(ID::CLR, sig_c);
+	cell->setPort(ID::Y, sig);
+	cell->set_src_attribute(src);
+	return sig;
+}
+
+RTLIL::Cell* RTLIL::Module::addSetTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src)
+{
+	Cell *cell = addCell(name, ID($set_tag));
+	cell->parameters[ID::WIDTH] = sig_a.size();
+	cell->parameters[ID::TAG] = tag;
+	cell->setPort(ID::A, sig_a);
+	cell->setPort(ID::SET, sig_s);
+	cell->setPort(ID::CLR, sig_c);
+	cell->setPort(ID::Y, sig_y);
+	cell->set_src_attribute(src);
+	return cell;
+}
+
+RTLIL::SigSpec RTLIL::Module::GetTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src)
+{
+	RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size());
+	Cell *cell = addCell(name, ID($get_tag));
+	cell->parameters[ID::WIDTH] = sig_a.size();
+	cell->parameters[ID::TAG] = tag;
+	cell->setPort(ID::A, sig_a);
+	cell->setPort(ID::Y, sig);
+	cell->set_src_attribute(src);
+	return sig;
+}
+
+RTLIL::Cell* RTLIL::Module::addOverwriteTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src)
+{
+	RTLIL::Cell *cell = addCell(name, ID($overwrite_tag));
+	cell->parameters[ID::WIDTH] = sig_a.size();
+	cell->parameters[ID::TAG] = tag;
+	cell->setPort(ID::A, sig_a);
+	cell->setPort(ID::SET, sig_s);
+	cell->setPort(ID::CLR, sig_c);
+	cell->set_src_attribute(src);
+	return cell;
+}
+
+RTLIL::SigSpec RTLIL::Module::OriginalTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src)
+{
+	RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size());
+	Cell *cell = addCell(name, ID($original_tag));
+	cell->parameters[ID::WIDTH] = sig_a.size();
+	cell->parameters[ID::TAG] = tag;
+	cell->setPort(ID::A, sig_a);
+	cell->setPort(ID::Y, sig);
+	cell->set_src_attribute(src);
+	return sig;
+}
+
+RTLIL::SigSpec RTLIL::Module::FutureFF(RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src)
+{
+	RTLIL::SigSpec sig = addWire(NEW_ID, sig_e.size());
+	Cell *cell = addCell(name, ID($future_ff));
+	cell->parameters[ID::WIDTH] = sig_e.size();
+	cell->setPort(ID::A, sig_e);
+	cell->setPort(ID::Y, sig);
+	cell->set_src_attribute(src);
+	return sig;
+}
+
 RTLIL::Wire::Wire()
 {
 	static unsigned int hashidx_count = 123456789;

kernel/rtlil.h

@@ -1465,6 +1465,13 @@ public:
 	RTLIL::SigSpec Allseq    (RTLIL::IdString name, int width = 1, const std::string &src = "");
 	RTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = "");
 
+	RTLIL::SigSpec SetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = "");
+	RTLIL::Cell*   addSetTag       (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = "");
+	RTLIL::SigSpec GetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = "");
+	RTLIL::Cell*   addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = "");
+	RTLIL::SigSpec OriginalTag     (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = "");
+	RTLIL::SigSpec FutureFF        (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = "");
+
 #ifdef WITH_PYTHON
 	static std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);
 #endif

passes/cmds/Makefile.inc

@@ -46,3 +46,5 @@ OBJS += passes/cmds/printattrs.o
 OBJS += passes/cmds/sta.o
 OBJS += passes/cmds/clean_zerowidth.o
 OBJS += passes/cmds/xprop.o
+OBJS += passes/cmds/dft_tag.o
+OBJS += passes/cmds/future.o

passes/cmds/future.cc

@@ -0,0 +1,140 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/celltypes.h"
+#include "kernel/ff.h"
+#include "kernel/ffinit.h"
+#include "kernel/modtools.h"
+#include "kernel/sigtools.h"
+#include "kernel/utils.h"
+#include "kernel/yosys.h"
+#include <deque>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct FutureOptions {
+};
+
+struct FutureWorker {
+	Module *module;
+	FutureOptions options;
+	ModWalker modwalker;
+	SigMap &sigmap;
+	FfInitVals initvals;
+
+	dict<SigBit, SigBit> future_ff_signals;
+
+	FutureWorker(Module *module, FutureOptions options) :
+		module(module), options(options), modwalker(module->design), sigmap(modwalker.sigmap)
+	{
+		modwalker.setup(module);
+		initvals.set(&modwalker.sigmap, module);
+
+		std::vector<Cell *> replaced_cells;
+		for (auto cell : module->selected_cells()) {
+			if (cell->type != ID($future_ff))
+				continue;
+
+			module->connect(cell->getPort(ID::Y), future_ff(cell->getPort(ID::A)));
+			replaced_cells.push_back(cell);
+		}
+
+		for (auto cell : replaced_cells) {
+			module->remove(cell);
+		}
+	}
+
+	SigSpec future_ff(SigSpec sig)
+	{
+		for (auto &bit : sig) {
+			bit = future_ff(bit);
+		}
+		return sig;
+	}
+
+	SigBit future_ff(SigBit bit)
+	{
+		if (!bit.is_wire())
+			return bit;
+
+		auto found = future_ff_signals.find(bit);
+		if (found != future_ff_signals.end())
+			return found->second;
+
+		auto found_driver = modwalker.signal_drivers.find(bit);
+		if (found_driver == modwalker.signal_drivers.end() || found_driver->second.size() < 1)
+			log_error("No driver for future_ff target signal %s found\n", log_signal(bit));
+		if (found_driver->second.size() > 1)
+			log_error("Found multiple drivers for future_ff target signal %s\n", log_signal(bit));
+		auto driver = *found_driver->second.begin();
+		if (!RTLIL::builtin_ff_cell_types().count(driver.cell->type) && driver.cell->type != ID($anyinit))
+			log_error("Driver for future_ff target signal %s has non-FF cell type %s\n", log_signal(bit), log_id(driver.cell->type));
+
+		FfData ff(&initvals, driver.cell);
+
+		if (!ff.has_clk && !ff.has_gclk)
+			log_error("Driver for future_ff target signal %s has cell type %s, which is not clocked\n", log_signal(bit),
+				  log_id(driver.cell->type));
+
+		ff.unmap_ce_srst();
+
+		// We insert all bits into the mapping, because unmap_ce_srst might
+		// have removed the cell which is still present in the modwalker data.
+		// By inserting all bits driven by th FF we ensure that we'll never use
+		// that stale modwalker data again.
+
+		for (int i = 0; i < ff.width; ++i) {
+			future_ff_signals.emplace(ff.sig_q[i], ff.sig_d[i]);
+		}
+
+		return future_ff_signals.at(bit);
+	}
+};
+
+struct FuturePass : public Pass {
+	FuturePass() : Pass("future", "resolve future sampled value functions") {}
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    future [options] [selection]\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		FutureOptions options;
+
+		log_header(design, "Executing FUTURE pass.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+
+			break;
+		}
+
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules()) {
+			FutureWorker worker(module, options);
+		}
+	}
+} FuturePass;
+
+PRIVATE_NAMESPACE_END

passes/opt/opt_clean.cc

@@ -76,6 +76,9 @@ struct keep_cache_t
 		if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
 			return true;
 
+		if (cell->type.in(ID($overwrite_tag)))
+			return true;
+
 		if (!ignore_specify && cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
 			return true;
 

techlibs/common/prep.cc

@@ -189,6 +189,7 @@ struct PrepPass : public ScriptPass
 				run(ifxmode ? "proc -ifx" : "proc");
 			if (help_mode || flatten)
 				run("flatten", "(if -flatten)");
+			run("future");
 			run(nokeepdc ? "opt_expr" : "opt_expr -keepdc");
 			run("opt_clean");
 			run("check");

techlibs/common/simlib.v

@@ -2671,3 +2671,73 @@ endmodule
 `endif
 
 // --------------------------------------------------------
+
+module \$set_tag (A, SET, CLR, Y);
+
+parameter TAG = "";
+parameter WIDTH = 0;
+
+input [WIDTH-1:0] A;
+input [WIDTH-1:0] SET;
+input [WIDTH-1:0] CLR;
+output [WIDTH-1:0] Y;
+
+assign Y = A;
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$get_tag (A, Y);
+
+parameter TAG = "";
+parameter WIDTH = 0;
+
+input [WIDTH-1:0] A;
+output [WIDTH-1:0] Y;
+
+assign Y = A;
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$overwrite_tag (A, SET, CLR);
+
+parameter TAG = "";
+parameter WIDTH = 0;
+
+input [WIDTH-1:0] A;
+input [WIDTH-1:0] SET;
+input [WIDTH-1:0] CLR;
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$original_tag (A, Y);
+
+parameter TAG = "";
+parameter WIDTH = 0;
+
+input [WIDTH-1:0] A;
+output [WIDTH-1:0] Y;
+
+assign Y = A;
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$future_ff (A, Y);
+
+parameter WIDTH = 0;
+
+input [WIDTH-1:0] A;
+output [WIDTH-1:0] Y;
+
+assign Y = A;
+
+endmodule
+
+// --------------------------------------------------------