mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-06 06:03:23 +00:00
After reading the SV spec, using non-standard predict() instead of expect()
This commit is contained in:
parent
721f1f5ecf
commit
d7763634b6
16 changed files with 28 additions and 32 deletions
|
@ -1017,7 +1017,7 @@ namespace {
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in("$assert", "$assume", "$expect")) {
|
||||
if (cell->type.in("$assert", "$assume", "$predict")) {
|
||||
port("\\A", 1);
|
||||
port("\\EN", 1);
|
||||
check_expected();
|
||||
|
@ -1798,7 +1798,7 @@ RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a
|
|||
|
||||
RTLIL::Cell* RTLIL::Module::addExpect(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
|
||||
{
|
||||
RTLIL::Cell *cell = addCell(name, "$expect");
|
||||
RTLIL::Cell *cell = addCell(name, "$predict");
|
||||
cell->setPort("\\A", sig_a);
|
||||
cell->setPort("\\EN", sig_en);
|
||||
return cell;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue