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After reading the SV spec, using non-standard predict() instead of expect()

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This commit is contained in:
Clifford Wolf 2016-07-21 13:34:33 +02:00
parent 721f1f5ecf
commit d7763634b6
16 changed files with 28 additions and 32 deletions
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6
frontends/verilog/verilog_lexer.l
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@ -63,6 +63,10 @@ YOSYS_NAMESPACE_END
frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \
return TOK_ID;
#define NON_KEYWORD() \
frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \
return TOK_ID;
#define YY_INPUT(buf,result,max_size) \
result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size)
@ -173,7 +177,7 @@ YOSYS_NAMESPACE_END
"assert" { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
"assume" { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
"expect" { if (formal_mode) return TOK_EXPECT; SV_KEYWORD(TOK_EXPECT); }
"predict" { if (formal_mode) return TOK_PREDICT; NON_KEYWORD(); }
"property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
"logic" { SV_KEYWORD(TOK_REG); }
"bit" { SV_KEYWORD(TOK_REG); }