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After reading the SV spec, using non-standard predict() instead of expect()

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Clifford Wolf 2016-07-21 13:34:33 +02:00
parent 721f1f5ecf
commit d7763634b6
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@ -384,8 +384,8 @@ from SystemVerilog:
form. In module context: "assert property (<expression>);" and within an
always block: "assert(<expression>);". It is transformed to a $assert cell.
- The "assume" and "expect" statements from SystemVerilog are also
supported. The same limitations as with the "assert" statement apply.
- The "assume" statements from SystemVerilog are also supported. The same
limitations as with the "assert" statement apply.
- The keywords "always_comb", "always_ff" and "always_latch", "logic" and
"bit" are supported.