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sv: support for parameters without default values

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- Modules with a parameter without a default value will be automatically
  deferred until the hierarchy pass
- Allows for parameters without defaults as module items, rather than
  just int the `parameter_port_list`, despite being forbidden in the LRM
- Check for parameters without defaults that haven't been overriden
- Add location info to parameter/localparam declarations
This commit is contained in:
Zachary Snow 2021-03-02 10:43:53 -05:00
parent 375af199ef
commit d738b2c127
12 changed files with 225 additions and 5 deletions
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24
frontends/verilog/verilog_parser.y
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@ -1462,7 +1462,26 @@ param_decl_list:
single_param_decl | param_decl_list ',' single_param_decl;
single_param_decl:
TOK_ID '=' expr {
single_param_decl_ident '=' expr {
AstNode *decl = ast_stack.back()->children.back();
log_assert(decl->type == AST_PARAMETER || decl->type == AST_LOCALPARAM);
delete decl->children[0];
decl->children[0] = $3;
} |
single_param_decl_ident {
AstNode *decl = ast_stack.back()->children.back();
if (decl->type != AST_PARAMETER) {
log_assert(decl->type == AST_LOCALPARAM);
frontend_verilog_yyerror("localparam initialization is missing!");
}
if (!sv_mode)
frontend_verilog_yyerror("Parameter defaults can only be omitted in SystemVerilog mode!");
delete decl->children[0];
decl->children.erase(decl->children.begin());
};
single_param_decl_ident:
TOK_ID {
AstNode *node;
if (astbuf1 == nullptr) {
if (!sv_mode)
@ -1473,10 +1492,9 @@ single_param_decl:
node = astbuf1->clone();
}
node->str = *$1;
delete node->children[0];
node->children[0] = $3;
ast_stack.back()->children.push_back(node);
delete $1;
SET_AST_NODE_LOC(node, @1, @1);
};
defparam_decl: