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https://github.com/YosysHQ/yosys
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sv: support for parameters without default values
- Modules with a parameter without a default value will be automatically deferred until the hierarchy pass - Allows for parameters without defaults as module items, rather than just int the `parameter_port_list`, despite being forbidden in the LRM - Check for parameters without defaults that haven't been overriden - Add location info to parameter/localparam declarations
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375af199ef
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d738b2c127
12 changed files with 225 additions and 5 deletions
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@ -968,6 +968,14 @@ void AST::set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast)
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obj->attributes[ID::src] = ast->loc_string();
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}
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static bool param_has_no_default(const AstNode *param) {
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const auto &children = param->children;
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log_assert(param->type == AST_PARAMETER);
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log_assert(children.size() <= 2);
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return children.empty() ||
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(children.size() == 1 && children[0]->type == AST_RANGE);
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}
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// create a new AstModule from an AST_MODULE AST node
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static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast = NULL, bool quiet = false)
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{
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@ -1006,6 +1014,10 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
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if (!defer)
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{
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for (const AstNode *node : ast->children)
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if (node->type == AST_PARAMETER && param_has_no_default(node))
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log_file_error(node->filename, node->location.first_line, "Parameter `%s' has no default value and has not been overridden!\n", node->str.c_str());
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bool blackbox_module = flag_lib;
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if (!blackbox_module && !flag_noblackbox) {
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@ -1229,7 +1241,18 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
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if (flag_icells && (*it)->str.compare(0, 2, "\\$") == 0)
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(*it)->str = (*it)->str.substr(1);
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if (defer)
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bool defer_local = defer;
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if (!defer_local)
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for (const AstNode *node : (*it)->children)
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if (node->type == AST_PARAMETER && param_has_no_default(node))
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{
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log("Deferring `%s' because it contains parameter(s) without defaults.\n", ast->str.c_str());
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defer_local = true;
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break;
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}
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if (defer_local)
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(*it)->str = "$abstract" + (*it)->str;
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if (design->has((*it)->str)) {
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@ -1248,7 +1271,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
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}
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}
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design->add(process_module(*it, defer));
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design->add(process_module(*it, defer_local));
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current_ast_mod = nullptr;
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}
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else if ((*it)->type == AST_PACKAGE) {
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@ -1619,6 +1642,8 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
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}
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continue;
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rewrite_parameter:
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if (param_has_no_default(child))
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child->children.insert(child->children.begin(), nullptr);
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delete child->children.at(0);
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if ((it->second.flags & RTLIL::CONST_FLAG_REAL) != 0) {
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child->children[0] = new AstNode(AST_REALVALUE);
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@ -1462,7 +1462,26 @@ param_decl_list:
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single_param_decl | param_decl_list ',' single_param_decl;
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single_param_decl:
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TOK_ID '=' expr {
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single_param_decl_ident '=' expr {
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AstNode *decl = ast_stack.back()->children.back();
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log_assert(decl->type == AST_PARAMETER || decl->type == AST_LOCALPARAM);
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delete decl->children[0];
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decl->children[0] = $3;
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} |
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single_param_decl_ident {
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AstNode *decl = ast_stack.back()->children.back();
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if (decl->type != AST_PARAMETER) {
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log_assert(decl->type == AST_LOCALPARAM);
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frontend_verilog_yyerror("localparam initialization is missing!");
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}
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if (!sv_mode)
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frontend_verilog_yyerror("Parameter defaults can only be omitted in SystemVerilog mode!");
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delete decl->children[0];
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decl->children.erase(decl->children.begin());
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};
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single_param_decl_ident:
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TOK_ID {
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AstNode *node;
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if (astbuf1 == nullptr) {
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if (!sv_mode)
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@ -1473,10 +1492,9 @@ single_param_decl:
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node = astbuf1->clone();
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}
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node->str = *$1;
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delete node->children[0];
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node->children[0] = $3;
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ast_stack.back()->children.push_back(node);
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delete $1;
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SET_AST_NODE_LOC(node, @1, @1);
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};
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defparam_decl:
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