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sv: support wand and wor of data types

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This enables the usage of declarations of wand or wor with a base type
of logic, integer, or a typename. Note that declarations of nets with
2-state base types is still permitted, in violation of the spec.
This commit is contained in:
Zachary Snow 2021-08-13 20:51:28 -07:00 • committed by Zachary Snow
parent 6b7267b849
commit d6fe6d4fb6
4 changed files with 53 additions and 10 deletions
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21
frontends/verilog/verilog_parser.y
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@ -832,16 +832,10 @@ opt_wire_type_token:
wire_type_token | %empty;
wire_type_token:
TOK_WOR {
astbuf3->is_wor = true;
// nets
net_type {
} |
TOK_WAND {
astbuf3->is_wand = true;
} |
// wires
TOK_WIRE {
} |
TOK_WIRE logic_type {
net_type logic_type {
} |
// regs
TOK_REG {
@ -868,6 +862,15 @@ wire_type_token:
astbuf3->range_right = 0;
};
net_type:
TOK_WOR {
astbuf3->is_wor = true;
} |
TOK_WAND {
astbuf3->is_wand = true;
} |
TOK_WIRE;
logic_type:
TOK_LOGIC {
} |