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rtlil: add const accessors for modules, wires, and cells

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This commit is contained in:
Zachary Snow 2021-03-24 11:23:23 -04:00 • committed by Zachary Snow
parent 4762ed90ff
commit d6d5c2ef34
2 changed files with 15 additions and 0 deletions
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5
kernel/rtlil.cc
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@ -580,6 +580,11 @@ RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
return modules_.count(name) ? modules_.at(name) : NULL; return modules_.count(name) ? modules_.at(name) : NULL;
} }
const RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name) const
{
return modules_.count(name) ? modules_.at(name) : NULL;
}
RTLIL::Module *RTLIL::Design::top_module() RTLIL::Module *RTLIL::Design::top_module()
{ {
RTLIL::Module *module = nullptr; RTLIL::Module *module = nullptr;

10
kernel/rtlil.h
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@ -1043,6 +1043,7 @@ struct RTLIL::Design
RTLIL::ObjRange<RTLIL::Module*> modules(); RTLIL::ObjRange<RTLIL::Module*> modules();
RTLIL::Module *module(RTLIL::IdString name); RTLIL::Module *module(RTLIL::IdString name);
const RTLIL::Module *module(RTLIL::IdString name) const;
RTLIL::Module *top_module(); RTLIL::Module *top_module();
bool has(RTLIL::IdString id) const { bool has(RTLIL::IdString id) const {
@ -1191,6 +1192,15 @@ public:
return it == cells_.end() ? nullptr : it->second; return it == cells_.end() ? nullptr : it->second;
} }
const RTLIL::Wire* wire(RTLIL::IdString id) const{
auto it = wires_.find(id);
return it == wires_.end() ? nullptr : it->second;
}
const RTLIL::Cell* cell(RTLIL::IdString id) const {
auto it = cells_.find(id);
return it == cells_.end() ? nullptr : it->second;
}
RTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); } RTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }
RTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); } RTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }