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rtlil: add const accessors for modules, wires, and cells

This commit is contained in:
Zachary Snow 2021-03-24 11:23:23 -04:00 committed by Zachary Snow
parent 4762ed90ff
commit d6d5c2ef34
2 changed files with 15 additions and 0 deletions

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@ -580,6 +580,11 @@ RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
return modules_.count(name) ? modules_.at(name) : NULL;
}
const RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name) const
{
return modules_.count(name) ? modules_.at(name) : NULL;
}
RTLIL::Module *RTLIL::Design::top_module()
{
RTLIL::Module *module = nullptr;