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rtlil: add const accessors for modules, wires, and cells
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2 changed files with 15 additions and 0 deletions
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@ -580,6 +580,11 @@ RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
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return modules_.count(name) ? modules_.at(name) : NULL;
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}
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const RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name) const
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{
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return modules_.count(name) ? modules_.at(name) : NULL;
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}
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RTLIL::Module *RTLIL::Design::top_module()
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{
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RTLIL::Module *module = nullptr;
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