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https://github.com/YosysHQ/yosys
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sim/formalff: Clock handling for yw cosim
This commit is contained in:
Jannis Harder
parent
7ddec5093f
commit
d6c7aa0e3d
5 changed files with 274 additions and 33 deletions
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@ -317,6 +317,172 @@ struct InitValWorker
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}
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};
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struct ReplacedPort {
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IdString name;
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int offset;
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bool clk_pol;
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};
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struct HierarchyWorker
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{
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Design *design;
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pool<Module *> pending;
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dict<Module *, std::vector<ReplacedPort>> replaced_clk_inputs;
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HierarchyWorker(Design *design) :
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design(design)
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{
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for (auto module : design->modules())
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pending.insert(module);
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}
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void propagate();
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const std::vector<ReplacedPort> &find_replaced_clk_inputs(IdString cell_type);
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};
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// Propagates replaced clock signals
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struct PropagateWorker
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{
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HierarchyWorker &hierarchy;
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Module *module;
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SigMap sigmap;
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dict<SigBit, bool> replaced_clk_bits;
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dict<SigBit, SigBit> not_drivers;
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std::vector<ReplacedPort> replaced_clk_inputs;
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std::vector<std::pair<SigBit, bool>> pending;
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PropagateWorker(Module *module, HierarchyWorker &hierarchy) :
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hierarchy(hierarchy), module(module), sigmap(module)
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{
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hierarchy.pending.erase(module);
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for (auto wire : module->wires())
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if (wire->has_attribute(ID::replaced_by_gclk))
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replace_clk_bit(SigBit(wire), wire->attributes[ID::replaced_by_gclk].bits.at(0) == State::S1, false);
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for (auto cell : module->cells()) {
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if (cell->type.in(ID($not), ID($_NOT_))) {
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auto sig_a = cell->getPort(ID::A);
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auto &sig_y = cell->getPort(ID::Y);
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sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
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for (int i = 0; i < GetSize(sig_a); i++)
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if (sig_a[i].is_wire())
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not_drivers.emplace(sigmap(sig_y[i]), sigmap(sig_a[i]));
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} else {
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for (auto &port_bit : hierarchy.find_replaced_clk_inputs(cell->type))
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replace_clk_bit(cell->getPort(port_bit.name)[port_bit.offset], port_bit.clk_pol, true);
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}
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}
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while (!pending.empty()) {
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auto current = pending.back();
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pending.pop_back();
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auto it = not_drivers.find(current.first);
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if (it == not_drivers.end())
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continue;
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replace_clk_bit(it->second, !current.second, true);
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}
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for (auto cell : module->cells()) {
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if (cell->type.in(ID($not), ID($_NOT_)))
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continue;
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for (auto &conn : cell->connections()) {
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if (!cell->output(conn.first))
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continue;
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for (SigBit bit : conn.second) {
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sigmap.apply(bit);
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if (replaced_clk_bits.count(bit))
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log_error("derived signal %s driven by %s (%s) from module %s is used as clock, derived clocks are only supported with clk2fflogic.\n",
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log_signal(bit), log_id(cell->name), log_id(cell->type), log_id(module));
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}
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}
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}
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for (auto port : module->ports) {
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auto wire = module->wire(port);
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if (!wire->port_input)
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continue;
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for (int i = 0; i < GetSize(wire); i++) {
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SigBit bit(wire, i);
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sigmap.apply(bit);
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auto it = replaced_clk_bits.find(bit);
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if (it == replaced_clk_bits.end())
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continue;
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replaced_clk_inputs.emplace_back(ReplacedPort {port, i, it->second});
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if (it->second) {
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bit = module->Not(NEW_ID, bit);
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}
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}
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}
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}
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void replace_clk_bit(SigBit bit, bool polarity, bool add_attribute)
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{
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sigmap.apply(bit);
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if (!bit.is_wire())
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log_error("XXX todo\n");
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auto it = replaced_clk_bits.find(bit);
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if (it != replaced_clk_bits.end()) {
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if (it->second != polarity)
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log_error("signal %s from module %s is used as clock with different polarities, run clk2fflogic instead.\n",
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log_signal(bit), log_id(module));
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return;
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}
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replaced_clk_bits.emplace(bit, polarity);
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if (add_attribute) {
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Wire *clk_wire = bit.wire;
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if (bit.offset != 0 || GetSize(bit.wire) != 1) {
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clk_wire = module->addWire(NEW_ID);
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module->connect(RTLIL::SigBit(clk_wire), bit);
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}
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clk_wire->attributes[ID::replaced_by_gclk] = polarity ? State::S1 : State::S0;
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clk_wire->set_bool_attribute(ID::keep);
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}
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pending.emplace_back(bit, polarity);
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}
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};
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const std::vector<ReplacedPort> &HierarchyWorker::find_replaced_clk_inputs(IdString cell_type)
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{
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static const std::vector<ReplacedPort> empty;
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if (!cell_type.isPublic())
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return empty;
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Module *module = design->module(cell_type);
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if (module == nullptr)
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return empty;
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auto it = replaced_clk_inputs.find(module);
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if (it != replaced_clk_inputs.end())
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return it->second;
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if (pending.count(module)) {
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PropagateWorker worker(module, *this);
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return replaced_clk_inputs.emplace(module, std::move(worker.replaced_clk_inputs)).first->second;
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}
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return empty;
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}
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void HierarchyWorker::propagate()
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{
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while (!pending.empty())
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PropagateWorker worker(pending.pop(), *this);
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}
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struct FormalFfPass : public Pass {
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FormalFfPass() : Pass("formalff", "prepare FFs for formal") { }
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void help() override
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@ -362,6 +528,15 @@ struct FormalFfPass : public Pass {
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log(" them. For -ff2anyinit, this reduces the number of generated $anyinit\n");
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log(" cells that drive wires with private names.\n");
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log("\n");
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log(" -hierarchy\n");
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log(" Propagates the 'replaced_by_gclk' attribute set by clk2ff upwards\n");
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log(" through the design hierarchy towards the toplevel inputs. This option\n");
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log(" works on the whole design and ignores the selection.\n");
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log("\n");
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log(" -assume\n");
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log(" Add assumptions that constrain wires with the 'replaced_by_gclk'\n");
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log(" attribute to the value they would have before an active clock edge.\n");
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log("\n");
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// TODO: An option to check whether all FFs use the same clock before changing it to the global clock
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}
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@ -372,6 +547,8 @@ struct FormalFfPass : public Pass {
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bool flag_anyinit2ff = false;
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bool flag_fine = false;
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bool flag_setundef = false;
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bool flag_hierarchy = false;
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bool flag_assume = false;
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log_header(design, "Executing FORMALFF pass.\n");
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@ -398,12 +575,20 @@ struct FormalFfPass : public Pass {
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flag_setundef = true;
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continue;
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}
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if (args[argidx] == "-hierarchy") {
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flag_hierarchy = true;
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continue;
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}
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if (args[argidx] == "-assume") {
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flag_assume = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!(flag_clk2ff || flag_ff2anyinit || flag_anyinit2ff))
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log_cmd_error("One of the options -clk2ff, -ff2anyinit, or -anyinit2ff must be specified.\n");
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if (!(flag_clk2ff || flag_ff2anyinit || flag_anyinit2ff || flag_hierarchy || flag_assume))
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log_cmd_error("One of the options -clk2ff, -ff2anyinit, -anyinit2ff, -hierarchy or -assume must be specified.\n");
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if (flag_ff2anyinit && flag_anyinit2ff)
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log_cmd_error("The options -ff2anyinit and -anyinit2ff are exclusive.\n");
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@ -548,6 +733,33 @@ struct FormalFfPass : public Pass {
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ff.emit();
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}
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}
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if (flag_hierarchy) {
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HierarchyWorker worker(design);
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worker.propagate();
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}
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if (flag_assume) {
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for (auto module : design->selected_modules()) {
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std::vector<pair<SigBit, bool>> found;
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for (auto wire : module->wires()) {
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if (!wire->has_attribute(ID::replaced_by_gclk))
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continue;
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bool clk_pol = wire->attributes[ID::replaced_by_gclk].bits.at(0) == State::S1;
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found.emplace_back(SigSpec(wire), clk_pol);
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}
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for (auto pair : found) {
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SigBit clk = pair.first;
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if (pair.second)
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clk = module->Not(NEW_ID, clk);
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module->addAssume(NEW_ID, clk, State::S1);
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}
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}
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}
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}
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} FormalFfPass;
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@ -1655,28 +1655,25 @@ struct SimWorker : SimShared
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};
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struct YwHierarchy {
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dict<IdPath, FoundYWPath> signal_paths;
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dict<IdPath, FoundYWPath> clock_paths;
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dict<IdPath, FoundYWPath> paths;
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};
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YwHierarchy prepare_yw_hierarchy(const ReadWitness &yw)
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{
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YwHierarchy hierarchy;
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pool<IdPath> paths;
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dict<IdPath, pool<IdString>> mem_paths;
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for (auto &signal : yw.signals)
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paths.insert(signal.path);
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for (auto &clock : yw.clocks) {
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if (paths.count(clock.path))
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log_warning("Witness path `%s` is present as witness signal and as clock, treating as clock and ignoring signal data.\n", clock.path.str().c_str());
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for (auto &clock : yw.clocks)
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paths.insert(clock.path);
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}
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for (auto &path : paths)
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if (path.has_address())
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mem_paths[path.prefix()].insert(path.back());
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YwHierarchy hierarchy;
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witness_hierarchy(top->module, top, [&](IdPath const &path, WitnessHierarchyItem item, SimInstance *instance) {
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if (item.cell != nullptr)
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return instance->children.at(item.cell);
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@ -1684,7 +1681,7 @@ struct SimWorker : SimShared
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if (paths.count(path)) {
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if (debug)
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log("witness hierarchy: found wire %s\n", path.str().c_str());
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bool inserted = hierarchy.signal_paths.emplace(path, {instance, item.wire, {}, INT_MIN}).second;
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bool inserted = hierarchy.paths.emplace(path, {instance, item.wire, {}, INT_MIN}).second;
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if (!inserted)
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log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str().c_str());
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}
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@ -1701,7 +1698,7 @@ struct SimWorker : SimShared
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word_path.get_address(addr);
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if (addr < item.mem->start_offset || (addr - item.mem->start_offset) >= item.mem->size)
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continue;
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bool inserted = hierarchy.signal_paths.emplace(word_path, {instance, nullptr, item.mem->memid, addr}).second;
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bool inserted = hierarchy.paths.emplace(word_path, {instance, nullptr, item.mem->memid, addr}).second;
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if (!inserted)
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log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str().c_str());
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}
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@ -1711,19 +1708,35 @@ struct SimWorker : SimShared
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});
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for (auto &path : paths)
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if (!hierarchy.signal_paths.count(path))
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if (!hierarchy.paths.count(path))
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log_warning("Yosys witness path `%s` was not found in this design, ignoring\n", path.str().c_str());
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dict<IdPath, dict<int, bool>> clock_inputs;
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for (auto &clock : yw.clocks) {
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auto found_path_it = hierarchy.signal_paths.find(clock.path);
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if (found_path_it == hierarchy.signal_paths.end())
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if (clock.is_negedge == clock.is_posedge)
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continue;
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hierarchy.clock_paths.insert(*found_path_it);
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hierarchy.signal_paths.erase(found_path_it);
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paths.insert(clock.path);
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clock_inputs[clock.path].emplace(clock.offset, clock.is_posedge);
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}
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for (auto &signal : yw.signals) {
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auto it = clock_inputs.find(signal.path);
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if (it == clock_inputs.end())
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continue;
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for (auto &clock_input : it->second) {
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int offset = clock_input.first;
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if (offset >= signal.offset && (offset - signal.offset) < signal.width) {
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int clock_bits_offset = signal.bits_offset + (offset - signal.offset);
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State expected = clock_input.second ? State::S0 : State::S1;
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for (int t = 0; t < GetSize(yw.steps); t++) {
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if (yw.get_bits(t, clock_bits_offset, 1) != expected)
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log_warning("Yosys witness trace has an unexpected value for the clock input `%s` in step %d.\n", signal.path.str().c_str(), t);
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}
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}
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}
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}
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// TODO add checks and warnings for witness signals (toplevel inputs, $any*) not present in the witness file
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return hierarchy;
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@ -1736,8 +1749,8 @@ struct SimWorker : SimShared
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for (auto &signal : yw.signals) {
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if (signal.init_only && t >= 1)
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continue;
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auto found_path_it = hierarchy.signal_paths.find(signal.path);
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if (found_path_it == hierarchy.signal_paths.end())
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auto found_path_it = hierarchy.paths.find(signal.path);
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if (found_path_it == hierarchy.paths.end())
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continue;
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auto &found_path = found_path_it->second;
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@ -1767,8 +1780,8 @@ struct SimWorker : SimShared
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for (auto &clock : yw.clocks) {
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if (clock.is_negedge == clock.is_posedge)
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continue;
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auto found_path_it = hierarchy.clock_paths.find(clock.path);
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if (found_path_it == hierarchy.clock_paths.end())
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auto found_path_it = hierarchy.paths.find(clock.path);
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if (found_path_it == hierarchy.paths.end())
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continue;
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auto &found_path = found_path_it->second;
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