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sim/formalff: Clock handling for yw cosim

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This commit is contained in:
Jannis Harder 2023-01-11 17:52:25 +01:00
parent 7ddec5093f
commit d6c7aa0e3d
5 changed files with 274 additions and 33 deletions
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2
backends/smt2/smt2.cc
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@ -998,7 +998,7 @@ struct Smt2Worker
if (contains_clock && GetSize(wire) == 1 && (clock_posedge.count(sig) || clock_negedge.count(sig)))
comments.push_back(stringf("; yosys-smt2-clock %s%s%s\n", get_id(wire),
clock_posedge.count(sig) ? " posedge" : "", clock_negedge.count(sig) ? " negedge" : ""));
if (contains_clock) {
if (wire->port_input && contains_clock) {
for (int i = 0; i < GetSize(sig); i++) {
bool is_posedge = clock_posedge.count(sig[i]);
bool is_negedge = clock_negedge.count(sig[i]);