pyosys: fix regressions from 0.58

- consistently use value semantics for objects passed along FFI boundary
  (not ideal but matches previous behavior)
- add new overload of RTLIL::Module: addMemory that does not require a "donor" object
  - the idea is `Module`, `Memory`, `Wire`, `Cell` and `Process` cannot be directly constructed in Python and can only be added to the existing memory hierarchy in `Design` using the `add` methods - `Memory` requiring a donor object was the odd one out here
- fix superclass member wrapping only looking at direct superclass for inheritance instead of recursively checking superclasses
- fix superclass member wrapping not using superclass's denylists
- fix Design's `__str__` function not returning a string
- fix the generator crashing if there's any `std::function` in a header
- misc: add a crude `__repr__` based on `__str__`

tests/pyosys/test_monitor.py

@@ -14,7 +14,7 @@ class Monitor(ys.Monitor):
 		self.mods.append(mod.name.str())
 
 m = Monitor()
-d.monitors.add(m)
+d.monitors = [m]
 
 ys.run_pass(f"read_verilog {__file_dir__ / 'spm.cut.v.gz'}", d)
 ys.run_pass("hierarchy -top spm", d)