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https://github.com/YosysHQ/yosys
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Rename satgen_algo.h -> algo.h, code cleanup and refactoring
This commit is contained in:
Bogdan Vukobratovic
parent
9892df17ef
commit
d69989b8d2
4 changed files with 264 additions and 278 deletions
239
kernel/algo.h
Normal file
239
kernel/algo.h
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@ -0,0 +1,239 @@
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/* -*- c++ -*-
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef SATGEN_ALGO_H
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#define SATGEN_ALGO_H
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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#include <stack>
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YOSYS_NAMESPACE_BEGIN
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CellTypes comb_cells_filt()
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{
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CellTypes ct;
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ct.setup_internals();
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ct.setup_stdcells();
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return ct;
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}
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struct Netlist {
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RTLIL::Module *module;
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SigMap sigmap;
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dict<RTLIL::SigBit, Cell *> sigbit_driver_map;
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dict<RTLIL::Cell *, std::set<RTLIL::SigBit>> cell_inputs_map;
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Netlist(RTLIL::Module *module) : module(module), sigmap(module)
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{
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CellTypes ct(module->design);
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setup_netlist(module, ct);
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}
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Netlist(RTLIL::Module *module, const CellTypes &ct) : module(module), sigmap(module) { setup_netlist(module, ct); }
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void setup_netlist(RTLIL::Module *module, const CellTypes &ct)
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{
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for (auto cell : module->cells()) {
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if (ct.cell_known(cell->type)) {
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std::set<RTLIL::SigBit> inputs, outputs;
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for (auto &port : cell->connections()) {
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std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector();
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if (ct.cell_output(cell->type, port.first))
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outputs.insert(bits.begin(), bits.end());
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else
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inputs.insert(bits.begin(), bits.end());
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}
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cell_inputs_map[cell] = inputs;
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for (auto &bit : outputs) {
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sigbit_driver_map[bit] = cell;
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};
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}
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}
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}
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};
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namespace detail
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{
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struct NetlistConeWireIter : public std::iterator<std::input_iterator_tag, const RTLIL::SigBit *> {
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using set_iter_t = std::set<RTLIL::SigBit>::iterator;
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const Netlist &net;
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const RTLIL::SigBit *p_sig;
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std::stack<std::pair<set_iter_t, set_iter_t>> dfs_path_stack;
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std::set<RTLIL::Cell *> cells_visited;
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NetlistConeWireIter(const Netlist &net, const RTLIL::SigBit *p_sig = NULL) : net(net), p_sig(p_sig) {}
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const RTLIL::SigBit &operator*() const { return *p_sig; };
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bool operator!=(const NetlistConeWireIter &other) const { return p_sig != other.p_sig; }
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bool operator==(const NetlistConeWireIter &other) const { return p_sig == other.p_sig; }
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void next_sig_in_dag()
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{
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while (1) {
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if (dfs_path_stack.empty()) {
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p_sig = NULL;
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return;
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}
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auto &cell_inputs_iter = dfs_path_stack.top().first;
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auto &cell_inputs_iter_guard = dfs_path_stack.top().second;
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cell_inputs_iter++;
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if (cell_inputs_iter != cell_inputs_iter_guard) {
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p_sig = &(*cell_inputs_iter);
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return;
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} else {
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dfs_path_stack.pop();
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}
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}
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}
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NetlistConeWireIter &operator++()
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{
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if (net.sigbit_driver_map.count(*p_sig)) {
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auto drv = net.sigbit_driver_map.at(*p_sig);
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if (!cells_visited.count(drv)) {
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auto &inputs = net.cell_inputs_map.at(drv);
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dfs_path_stack.push(std::make_pair(inputs.begin(), inputs.end()));
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cells_visited.insert(drv);
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p_sig = &(*dfs_path_stack.top().first);
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} else {
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next_sig_in_dag();
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}
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} else {
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next_sig_in_dag();
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}
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return *this;
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}
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};
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struct NetlistConeWireIterable {
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const Netlist &net;
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const RTLIL::SigBit *p_sig;
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NetlistConeWireIterable(const Netlist &net, const RTLIL::SigBit *p_sig) : net(net), p_sig(p_sig) {}
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NetlistConeWireIter begin() { return NetlistConeWireIter(net, p_sig); }
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NetlistConeWireIter end() { return NetlistConeWireIter(net); }
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};
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struct NetlistConeCellIter : public std::iterator<std::input_iterator_tag, const RTLIL::Cell *> {
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const Netlist &net;
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const RTLIL::SigBit *p_sig;
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NetlistConeWireIter sig_iter;
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NetlistConeCellIter(const Netlist &net, const RTLIL::SigBit *p_sig = NULL) : net(net), p_sig(p_sig), sig_iter(net, p_sig)
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{
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if ((p_sig != NULL) && (!has_driver_cell(*sig_iter))) {
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++(*this);
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}
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}
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bool has_driver_cell(const RTLIL::SigBit &s) { return net.sigbit_driver_map.count(s); }
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RTLIL::Cell *operator*() const { return net.sigbit_driver_map.at(*sig_iter); };
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bool operator!=(const NetlistConeCellIter &other) const { return sig_iter != other.sig_iter; }
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bool operator==(const NetlistConeCellIter &other) const { return sig_iter == other.sig_iter; }
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NetlistConeCellIter &operator++()
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{
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while (true) {
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++sig_iter;
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if (sig_iter.p_sig == NULL) {
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return *this;
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}
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if (has_driver_cell(*sig_iter)) {
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auto cell = net.sigbit_driver_map.at(*sig_iter);
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if (!sig_iter.cells_visited.count(cell)) {
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return *this;
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}
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}
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};
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}
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};
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struct NetlistConeCellIterable {
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const Netlist &net;
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const RTLIL::SigBit *p_sig;
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NetlistConeCellIterable(const Netlist &net, const RTLIL::SigBit *p_sig) : net(net), p_sig(p_sig) {}
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NetlistConeCellIter begin() { return NetlistConeCellIter(net, p_sig); }
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NetlistConeCellIter end() { return NetlistConeCellIter(net); }
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};
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struct NetlistConeInputsIter : public std::iterator<std::input_iterator_tag, const RTLIL::Cell *> {
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const Netlist &net;
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const RTLIL::SigBit *p_sig;
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NetlistConeWireIter sig_iter;
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bool has_driver_cell(const RTLIL::SigBit &s) { return net.sigbit_driver_map.count(s); }
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NetlistConeInputsIter(const Netlist &net, const RTLIL::SigBit *p_sig = NULL) : net(net), p_sig(p_sig), sig_iter(net, p_sig)
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{
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if ((p_sig != NULL) && (has_driver_cell(*sig_iter))) {
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++(*this);
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}
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}
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const RTLIL::SigBit &operator*() const { return *sig_iter; };
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bool operator!=(const NetlistConeInputsIter &other) const { return sig_iter != other.sig_iter; }
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bool operator==(const NetlistConeInputsIter &other) const { return sig_iter == other.sig_iter; }
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NetlistConeInputsIter &operator++()
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{
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do {
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++sig_iter;
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if (sig_iter.p_sig == NULL) {
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return *this;
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}
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} while (has_driver_cell(*sig_iter));
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return *this;
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}
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};
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struct NetlistConeInputsIterable {
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const Netlist &net;
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const RTLIL::SigBit *p_sig;
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NetlistConeInputsIterable(const Netlist &net, const RTLIL::SigBit *p_sig) : net(net), p_sig(p_sig) {}
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NetlistConeInputsIter begin() { return NetlistConeInputsIter(net, p_sig); }
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NetlistConeInputsIter end() { return NetlistConeInputsIter(net); }
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};
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} // namespace detail
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detail::NetlistConeWireIterable cone(const Netlist &net, const RTLIL::SigBit &sig) { return detail::NetlistConeWireIterable(net, &sig); }
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// detail::NetlistConeInputsIterable cone_inputs(const RTLIL::SigBit &sig) { return NetlistConeInputsIterable(this, &sig); }
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detail::NetlistConeCellIterable cell_cone(const Netlist &net, const RTLIL::SigBit &sig) { return detail::NetlistConeCellIterable(net, &sig); }
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YOSYS_NAMESPACE_END
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#endif
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@ -246,24 +246,24 @@ struct CellTypes
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cell_types.clear();
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}
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bool cell_known(RTLIL::IdString type)
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bool cell_known(RTLIL::IdString type) const
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{
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return cell_types.count(type) != 0;
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}
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bool cell_output(RTLIL::IdString type, RTLIL::IdString port)
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bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const
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{
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.outputs.count(port) != 0;
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}
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bool cell_input(RTLIL::IdString type, RTLIL::IdString port)
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bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const
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{
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.inputs.count(port) != 0;
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}
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bool cell_evaluable(RTLIL::IdString type)
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bool cell_evaluable(RTLIL::IdString type) const
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{
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.is_evaluable;
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@ -482,4 +482,3 @@ extern CellTypes yosys_celltypes;
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YOSYS_NAMESPACE_END
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#endif
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@ -1,201 +0,0 @@
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/* -*- c++ -*-
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef SATGEN_ALGO_H
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#define SATGEN_ALGO_H
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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#include <stack>
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YOSYS_NAMESPACE_BEGIN
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struct DriverMap : public std::map<RTLIL::SigBit, std::pair<RTLIL::Cell *, std::set<RTLIL::SigBit>>> {
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RTLIL::Module *module;
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SigMap sigmap;
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using map_t = std::map<RTLIL::SigBit, std::pair<RTLIL::Cell *, std::set<RTLIL::SigBit>>>;
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struct DriverMapConeWireIterator : public std::iterator<std::input_iterator_tag, const RTLIL::SigBit *> {
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using set_iter_t = std::set<RTLIL::SigBit>::iterator;
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DriverMap *drvmap;
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const RTLIL::SigBit *sig;
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std::stack<std::pair<set_iter_t, set_iter_t>> dfs;
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DriverMapConeWireIterator(DriverMap *drvmap) : DriverMapConeWireIterator(drvmap, NULL) {}
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DriverMapConeWireIterator(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig) {}
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inline const RTLIL::SigBit &operator*() const { return *sig; };
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inline bool operator!=(const DriverMapConeWireIterator &other) const { return sig != other.sig; }
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inline bool operator==(const DriverMapConeWireIterator &other) const { return sig == other.sig; }
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inline void operator++()
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{
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if (drvmap->count(*sig)) {
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std::pair<RTLIL::Cell *, std::set<RTLIL::SigBit>> &drv = drvmap->at(*sig);
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dfs.push(std::make_pair(drv.second.begin(), drv.second.end()));
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sig = &(*dfs.top().first);
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} else {
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while (1) {
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auto &inputs_iter = dfs.top();
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inputs_iter.first++;
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if (inputs_iter.first != inputs_iter.second) {
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sig = &(*inputs_iter.first);
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return;
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} else {
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dfs.pop();
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if (dfs.empty()) {
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sig = NULL;
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return;
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}
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}
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}
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}
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}
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};
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struct DriverMapConeWireIterable {
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DriverMap *drvmap;
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const RTLIL::SigBit *sig;
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DriverMapConeWireIterable(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig) {}
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inline DriverMapConeWireIterator begin() { return DriverMapConeWireIterator(drvmap, sig); }
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inline DriverMapConeWireIterator end() { return DriverMapConeWireIterator(drvmap); }
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};
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struct DriverMapConeCellIterator : public std::iterator<std::input_iterator_tag, const RTLIL::Cell *> {
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DriverMap *drvmap;
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const RTLIL::SigBit *sig;
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DriverMapConeWireIterator sig_iter;
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DriverMapConeCellIterator(DriverMap *drvmap) : DriverMapConeCellIterator(drvmap, NULL) {}
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DriverMapConeCellIterator(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig), sig_iter(drvmap, sig)
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{
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if ((sig != NULL) && (!drvmap->count(*sig_iter))) {
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++(*this);
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}
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}
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inline RTLIL::Cell *operator*() const
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{
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std::pair<RTLIL::Cell *, std::set<RTLIL::SigBit>> &drv = drvmap->at(*sig_iter);
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return drv.first;
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};
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inline bool operator!=(const DriverMapConeCellIterator &other) const { return sig_iter != other.sig_iter; }
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inline bool operator==(const DriverMapConeCellIterator &other) const { return sig_iter == other.sig_iter; }
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inline void operator++()
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{
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do {
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++sig_iter;
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if (sig_iter.sig == NULL) {
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return;
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}
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} while (!drvmap->count(*sig_iter));
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}
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};
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struct DriverMapConeCellIterable {
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DriverMap *drvmap;
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const RTLIL::SigBit *sig;
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DriverMapConeCellIterable(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig) {}
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inline DriverMapConeCellIterator begin() { return DriverMapConeCellIterator(drvmap, sig); }
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inline DriverMapConeCellIterator end() { return DriverMapConeCellIterator(drvmap); }
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};
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struct DriverMapConeInputsIterator : public std::iterator<std::input_iterator_tag, const RTLIL::Cell *> {
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DriverMap *drvmap;
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const RTLIL::SigBit *sig;
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DriverMapConeWireIterator sig_iter;
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DriverMapConeInputsIterator(DriverMap *drvmap) : DriverMapConeInputsIterator(drvmap, NULL) {}
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DriverMapConeInputsIterator(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig), sig_iter(drvmap, sig)
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{
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if ((sig != NULL) && (drvmap->count(*sig_iter))) {
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++(*this);
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}
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}
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inline const RTLIL::SigBit& operator*() const
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{
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return *sig_iter;
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};
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inline bool operator!=(const DriverMapConeInputsIterator &other) const { return sig_iter != other.sig_iter; }
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inline bool operator==(const DriverMapConeInputsIterator &other) const { return sig_iter == other.sig_iter; }
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inline void operator++()
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{
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do {
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++sig_iter;
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if (sig_iter.sig == NULL) {
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return;
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}
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} while (drvmap->count(*sig_iter));
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}
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};
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struct DriverMapConeInputsIterable {
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DriverMap *drvmap;
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const RTLIL::SigBit *sig;
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DriverMapConeInputsIterable(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig) {}
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|
||||
inline DriverMapConeInputsIterator begin() { return DriverMapConeInputsIterator(drvmap, sig); }
|
||||
inline DriverMapConeInputsIterator end() { return DriverMapConeInputsIterator(drvmap); }
|
||||
};
|
||||
|
||||
DriverMap(RTLIL::Module *module) : module(module), sigmap(module)
|
||||
{
|
||||
CellTypes ct;
|
||||
ct.setup_internals();
|
||||
ct.setup_stdcells();
|
||||
|
||||
for (auto &it : module->cells_) {
|
||||
if (ct.cell_known(it.second->type)) {
|
||||
std::set<RTLIL::SigBit> inputs, outputs;
|
||||
for (auto &port : it.second->connections()) {
|
||||
std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector();
|
||||
if (ct.cell_output(it.second->type, port.first))
|
||||
outputs.insert(bits.begin(), bits.end());
|
||||
else
|
||||
inputs.insert(bits.begin(), bits.end());
|
||||
}
|
||||
std::pair<RTLIL::Cell *, std::set<RTLIL::SigBit>> drv(it.second, inputs);
|
||||
for (auto &bit : outputs)
|
||||
(*this)[bit] = drv;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DriverMapConeWireIterable cone(const RTLIL::SigBit &sig) { return DriverMapConeWireIterable(this, &sig); }
|
||||
DriverMapConeInputsIterable cone_inputs(const RTLIL::SigBit &sig) { return DriverMapConeInputsIterable(this, &sig); }
|
||||
DriverMapConeCellIterable cell_cone(const RTLIL::SigBit &sig) { return DriverMapConeCellIterable(this, &sig); }
|
||||
};
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue