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https://github.com/YosysHQ/yosys
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Changed more code to the new RTLIL::Wire constructors
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parent
946ddff9ce
commit
d68c993ed2
8 changed files with 52 additions and 81 deletions
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@ -729,13 +729,10 @@ struct ExtractPass : public Pass {
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int portCounter = 1;
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for (auto wire : wires) {
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RTLIL::Wire *newWire = new RTLIL::Wire;
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newWire->name = wire->name;
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newWire->width = wire->width;
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RTLIL::Wire *newWire = newMod->addWire(wire->name, wire->width);
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newWire->port_id = portCounter++;
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newWire->port_input = true;
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newWire->port_output = true;
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newMod->add(newWire);
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}
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for (auto cell : cells) {
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@ -164,13 +164,8 @@ struct IopadmapPass : public Pass {
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log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str());
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RTLIL::Wire *new_wire = NULL;
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if (!portname2.empty()) {
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new_wire = new RTLIL::Wire;
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*new_wire = *wire;
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wire->name = NEW_ID;
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module->wires[wire->name] = wire;
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module->wires[new_wire->name] = new_wire;
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}
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if (!portname2.empty())
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new_wire = module->addWire(NEW_ID, wire);
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if (flag_bits)
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{
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@ -128,14 +128,14 @@ struct TechmapWorker
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for (auto &it : tpl->wires) {
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if (it.second->port_id > 0)
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positional_ports[stringf("$%d", it.second->port_id)] = it.first;
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RTLIL::Wire *w = new RTLIL::Wire(*it.second);
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apply_prefix(cell->name, w->name);
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std::string w_name = it.second->name;
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apply_prefix(cell->name, w_name);
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RTLIL::Wire *w = module->addWire(w_name, it.second);
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w->port_input = false;
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w->port_output = false;
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w->port_id = 0;
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if (it.second->get_bool_attribute("\\_techmap_special_"))
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w->attributes.clear();
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module->add(w);
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design->select(module, w);
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}
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@ -381,7 +381,6 @@ struct TechmapWorker
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log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
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techmap_wire_names.erase(it.first);
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tpl->wires.erase(data.wire->name);
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const char *p = data.wire->name.c_str();
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const char *q = strrchr(p+1, '.');
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@ -391,8 +390,7 @@ struct TechmapWorker
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std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
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while (tpl->wires.count(new_name))
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new_name += "_";
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data.wire->name = new_name;
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tpl->add(data.wire);
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tpl->rename(data.wire, new_name);
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std::string cmd_string = data.value.as_const().decode_string();
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Pass::call_on_module(map, tpl, cmd_string);
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