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Changed more code to the new RTLIL::Wire constructors

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This commit is contained in:
Clifford Wolf 2014-07-26 21:16:05 +02:00
parent 946ddff9ce
commit d68c993ed2
8 changed files with 52 additions and 81 deletions
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10
passes/cmds/splice.cc
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@ -224,14 +224,14 @@ struct SpliceWorker
for (auto &it : rework_wires)
{
module->wires.erase(it.first->name);
RTLIL::Wire *new_port = new RTLIL::Wire(*it.first);
it.first->name = NEW_ID;
std::string orig_name = it.first->name;
module->rename(it.first, NEW_ID);
RTLIL::Wire *new_port = module->addWire(orig_name, it.first);
it.first->port_id = 0;
it.first->port_input = false;
it.first->port_output = false;
module->add(it.first);
module->add(new_port);
module->connect(RTLIL::SigSig(new_port, it.second));
}
}