mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-04 10:20:24 +00:00
Code Activity

Changed more code to the new RTLIL::Wire constructors

Browse source
This commit is contained in:
Clifford Wolf 2014-07-26 21:16:05 +02:00
parent 946ddff9ce
commit d68c993ed2
8 changed files with 52 additions and 81 deletions
Download patch file Download diff file Expand all files Collapse all files

14
passes/cmds/rename.cc
View file

@ -31,21 +31,15 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
for (auto &it : module->wires)
if (it.first == from_name) {
RTLIL::Wire *wire = it.second;
log("Renaming wire %s to %s in module %s.\n", wire->name.c_str(), to_name.c_str(), module->name.c_str());
module->wires.erase(wire->name);
wire->name = to_name;
module->add(wire);
log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
module->rename(it.second, to_name);
return;
}
for (auto &it : module->cells)
if (it.first == from_name) {
RTLIL::Cell *cell = it.second;
log("Renaming cell %s to %s in module %s.\n", cell->name.c_str(), to_name.c_str(), module->name.c_str());
module->cells.erase(cell->name);
cell->name = to_name;
module->add(cell);
log("Renaming cell %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
module->rename(it.second, to_name);
return;
}

10
passes/cmds/splice.cc
View file

@ -224,14 +224,14 @@ struct SpliceWorker
for (auto &it : rework_wires)
{
module->wires.erase(it.first->name);
RTLIL::Wire *new_port = new RTLIL::Wire(*it.first);
it.first->name = NEW_ID;
std::string orig_name = it.first->name;
module->rename(it.first, NEW_ID);
RTLIL::Wire *new_port = module->addWire(orig_name, it.first);
it.first->port_id = 0;
it.first->port_input = false;
it.first->port_output = false;
module->add(it.first);
module->add(new_port);
module->connect(RTLIL::SigSig(new_port, it.second));
}
}