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Changed more code to the new RTLIL::Wire constructors
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parent
946ddff9ce
commit
d68c993ed2
8 changed files with 52 additions and 81 deletions
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@ -777,7 +777,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
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new_mod->attributes = attributes;
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for (auto &it : wires)
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new_mod->wires[it.first] = new RTLIL::Wire(*it.second);
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new_mod->addWire(it.first, it.second);
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for (auto &it : memories)
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new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
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@ -952,6 +952,18 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
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return wire;
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}
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RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
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{
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RTLIL::Wire *wire = addWire(name);
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wire->width = other->width;
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wire->start_offset = other->start_offset;
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wire->port_id = other->port_id;
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wire->port_input = other->port_input;
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wire->port_output = other->port_output;
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wire->attributes = other->attributes;
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return wire;
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}
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RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
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{
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RTLIL::Cell *cell = new RTLIL::Cell;
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