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https://github.com/YosysHQ/yosys
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fabulous: remove legacy -vpr option
Signed-off-by: Leo Moser <leomoser99@gmail.com>
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parent
32bd3e5418
commit
d671de97e9
1 changed files with 2 additions and 11 deletions
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@ -55,9 +55,6 @@ struct SynthPass : public ScriptPass
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log(" -lut <k>\n");
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log(" perform synthesis for a k-LUT architecture (default 4).\n");
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log("\n");
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log(" -vpr\n");
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log(" perform synthesis for the FABulous VPR flow (using slightly different techmapping).\n");
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log("\n");
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log(" -plib <primitive_library.v>\n");
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log(" use the specified Verilog file as a primitive library.\n");
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log("\n");
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@ -118,7 +115,7 @@ struct SynthPass : public ScriptPass
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string top_module, json_file, blif_file, plib, fsm_opts, memory_opts, carry_mode;
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std::vector<string> extra_plib, extra_map;
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bool autotop, forvpr, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten;
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bool autotop, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten;
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int lut;
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void clear_flags() override
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@ -127,7 +124,6 @@ struct SynthPass : public ScriptPass
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plib.clear();
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autotop = false;
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lut = 4;
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forvpr = false;
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noalumacc = false;
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nofsm = false;
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noshare = false;
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@ -170,10 +166,6 @@ struct SynthPass : public ScriptPass
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}
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continue;
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}
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if (args[argidx] == "-vpr") {
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forvpr = true;
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continue;
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}
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if (args[argidx] == "-auto-top") {
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autotop = true;
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continue;
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@ -371,8 +363,7 @@ struct SynthPass : public ScriptPass
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}
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if (check_label("map_cells")) {
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if (!forvpr)
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run(stringf("techmap -D LUT_K=%d -map +/fabulous/cells_map.v", lut));
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run(stringf("techmap -D LUT_K=%d -map +/fabulous/cells_map.v", lut));
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run("clean");
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}
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if (check_label("check")) {
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