diff --git a/tests/aiger/generate_mk.py b/tests/aiger/generate_mk.py index 0e0200d6d..eecee82fa 100644 --- a/tests/aiger/generate_mk.py +++ b/tests/aiger/generate_mk.py @@ -25,7 +25,7 @@ def create_tests(): b = base(aag) cmd = [ - f"$(ABC) -q \"read -c {b}.aig; write {b}_ref.v\" >/dev/null 2>&1;", + f"$(ABC) -q \"read -c {b}.aig; write {b}_ref.v\";", "$(YOSYS) -qp \"", f"read_verilog {b}_ref.v;", "prep;", @@ -37,7 +37,7 @@ def create_tests(): "design -import gate -as gate;", "miter -equiv -flatten -make_assert -make_outputs gold gate miter;", "sat -verify -prove-asserts -show-ports -seq 16 miter;", - f"\" -l {aag}.log >/dev/null 2>&1" + f"\" -l {aag}.log" ] gen_tests_makefile.generate_cmd_test(aag, cmd) @@ -47,7 +47,7 @@ def create_tests(): gen_tests_makefile.generate_ys_test(ys) cmd = [ "rm -rf gate; mkdir gate;", - "$(YOSYS) --no-version -p \"test_cell -aigmap -w gate/ -n 1 -s 1 all\" >/dev/null 2>&1;", + "$(YOSYS) --no-version -p \"test_cell -aigmap -w gate/ -n 1 -s 1 all\";", "set -o pipefail; diff --brief gold gate | tee aigmap.err;", "rm -f aigmap.err" ] diff --git a/tests/arch/generate_mk.py b/tests/arch/generate_mk.py index 3ea1f1c44..4c12a497c 100644 --- a/tests/arch/generate_mk.py +++ b/tests/arch/generate_mk.py @@ -27,18 +27,18 @@ def archs(): if arch_name in defines: for defn in defines[arch_name]: target_name = f"{target_base}_{defn}" - cmd = f"iverilog -t null -I{arch} -D{defn} -DNO_ICE40_DEFAULT_ASSIGNMENTS {path_str} >/dev/null 2>&1" + cmd = f"iverilog -t null -I{arch} -D{defn} -DNO_ICE40_DEFAULT_ASSIGNMENTS {path_str}" gen_tests_makefile.generate_target(target_name, cmd) else: target_name = f"{target_base}" - cmd = f"iverilog -t null -I{arch} -g2005-sv {path_str} >/dev/null 2>&1" + cmd = f"iverilog -t null -I{arch} -g2005-sv {path_str}" gen_tests_makefile.generate_target(target_name, cmd) def common(): for path in ["../../techlibs/common/simcells.v", "../../techlibs/common/simlib.v"]: path_obj = Path(path) target_name = path_obj.stem - cmd = f"iverilog -t null {path} >/dev/null 2>&1" + cmd = f"iverilog -t null {path}" gen_tests_makefile.generate_target(target_name, cmd) def main(): diff --git a/tests/bram/generate_mk.py b/tests/bram/generate_mk.py index a18972703..09f5c650b 100644 --- a/tests/bram/generate_mk.py +++ b/tests/bram/generate_mk.py @@ -320,7 +320,7 @@ def create_tests(): if i != j: gen_tests_makefile.generate_cmd_test( f"bram_{i}_{j}", - f"bash run-single.sh {i} {j} >/dev/null 2>&1" + f"bash run-single.sh {i} {j}" ) gen_tests_makefile.generate_custom(create_tests) diff --git a/tests/common.mk b/tests/common.mk index 9d45e3762..044054e0c 100644 --- a/tests/common.mk +++ b/tests/common.mk @@ -8,7 +8,7 @@ endif define run_test @set -e; \ rc=0; \ - ( set -e; $(2) ) || rc=$$?; \ + ( set -e; $(2) ) >/dev/null 2>&1 || rc=$$?; \ if [ $$rc -eq 0 ]; then \ echo "PASS $1"; \ echo PASS > $1.result; \ diff --git a/tests/cxxrtl/generate_mk.py b/tests/cxxrtl/generate_mk.py index a23e08a43..fceeb5188 100644 --- a/tests/cxxrtl/generate_mk.py +++ b/tests/cxxrtl/generate_mk.py @@ -8,12 +8,12 @@ import gen_tests_makefile def run_subtest(name): gen_tests_makefile.generate_cmd_test(f"cxxrtl_{name}", [ f"$${{CXX:-g++}} -std=c++11 -O2 -o cxxrtl-test-{name} -I../../backends/cxxrtl/runtime test_{name}.cc -lstdc++;", - f"./cxxrtl-test-{name} >/dev/null 2>&1", + f"./cxxrtl-test-{name}", ]) def compile_only(): gen_tests_makefile.generate_cmd_test("cxxrtl_unconnected_output", [ - '$(YOSYS) -p "read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc" >/dev/null 2>&1;', + '$(YOSYS) -p "read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc";', f'$${{CXX:-g++}} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc', ]) diff --git a/tests/fmt/generate_mk.py b/tests/fmt/generate_mk.py index e4b32f9e3..61f78c6af 100644 --- a/tests/fmt/generate_mk.py +++ b/tests/fmt/generate_mk.py @@ -29,8 +29,8 @@ def always_display(): for name, defs in cases: gen_tests_makefile.generate_target(f"always_display_{name}", cmd([ - f"$(YOSYS) -p \"read_verilog {defs} always_display.v; proc; opt_expr -mux_bool; clean\" -o yosys-always_display-{name}-1.v >/dev/null 2>&1", - f"$(YOSYS) -p \"read_verilog yosys-always_display-{name}-1.v; proc; opt_expr -mux_bool; clean\" -o yosys-always_display-{name}-2.v >/dev/null 2>&1", + f"$(YOSYS) -p \"read_verilog {defs} always_display.v; proc; opt_expr -mux_bool; clean\" -o yosys-always_display-{name}-1.v", + f"$(YOSYS) -p \"read_verilog yosys-always_display-{name}-1.v; proc; opt_expr -mux_bool; clean\" -o yosys-always_display-{name}-2.v", f"diff yosys-always_display-{name}-1.v yosys-always_display-{name}-2.v", ])) @@ -49,17 +49,17 @@ def roundtrip(): for name, defs in cases: gen_tests_makefile.generate_target(f"roundtrip_{name}", cmd([ - f"$(YOSYS) -p \"read_verilog {defs} roundtrip.v; proc; clean\" -o yosys-roundtrip-{name}-1.v >/dev/null 2>&1", - f"$(YOSYS) -p \"read_verilog yosys-roundtrip-{name}-1.v; proc; clean\" -o yosys-roundtrip-{name}-2.v >/dev/null 2>&1", + f"$(YOSYS) -p \"read_verilog {defs} roundtrip.v; proc; clean\" -o yosys-roundtrip-{name}-1.v", + f"$(YOSYS) -p \"read_verilog yosys-roundtrip-{name}-1.v; proc; clean\" -o yosys-roundtrip-{name}-2.v", f"diff yosys-roundtrip-{name}-1.v yosys-roundtrip-{name}-2.v", - f"iverilog {defs} -o iverilog-roundtrip-{name} roundtrip.v roundtrip_tb.v >/dev/null 2>&1", + f"iverilog {defs} -o iverilog-roundtrip-{name} roundtrip.v roundtrip_tb.v", f"./iverilog-roundtrip-{name} >iverilog-roundtrip-{name}.log", - f"iverilog {defs} -o iverilog-roundtrip-{name}-1 yosys-roundtrip-{name}-1.v roundtrip_tb.v >/dev/null 2>&1", + f"iverilog {defs} -o iverilog-roundtrip-{name}-1 yosys-roundtrip-{name}-1.v roundtrip_tb.v", f"./iverilog-roundtrip-{name}-1 >iverilog-roundtrip-{name}-1.log", - f"iverilog {defs} -o iverilog-roundtrip-{name}-2 yosys-roundtrip-{name}-2.v roundtrip_tb.v >/dev/null 2>&1", + f"iverilog {defs} -o iverilog-roundtrip-{name}-2 yosys-roundtrip-{name}-2.v roundtrip_tb.v", f"./iverilog-roundtrip-{name}-2 >iverilog-roundtrip-{name}-2.log", f"diff iverilog-roundtrip-{name}.log iverilog-roundtrip-{name}-1.log", @@ -72,11 +72,11 @@ def cxxrtl(): for name in cases: gen_tests_makefile.generate_target(f"cxxrtl_{name}", cmd([ - f"$(YOSYS) -p \"read_verilog {name}.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-{name}.cc\" >/dev/null 2>&1", + f"$(YOSYS) -p \"read_verilog {name}.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-{name}.cc\"", f"$${{CXX:-g++}} -std=c++11 -o yosys-{name} -I../../backends/cxxrtl/runtime {name}_tb.cc -lstdc++", f"./yosys-{name} 2>yosys-{name}.log", - f"iverilog -o iverilog-{name} {name}.v {name}_tb.v >/dev/null 2>&1", + f"iverilog -o iverilog-{name} {name}.v {name}_tb.v", f"./iverilog-{name} | grep -v \"$finish called\" >iverilog-{name}.log", f"diff iverilog-{name}.log yosys-{name}.log", @@ -85,21 +85,21 @@ def cxxrtl(): def extra(): gen_tests_makefile.generate_target("always_full_equiv", cmd([ - "$(YOSYS) -p \"read_verilog always_full.v; prep; clean\" -o yosys-always_full-1.v >/dev/null 2>&1", - "iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v >/dev/null 2>&1", + "$(YOSYS) -p \"read_verilog always_full.v; prep; clean\" -o yosys-always_full-1.v", + "iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v", "./iverilog-always_full-1 | grep -v \"$finish called\" >iverilog-always_full-1.log", "diff iverilog-always_full.log iverilog-always_full-1.log", ])) gen_tests_makefile.generate_target("display_lm", cmd([ "$(YOSYS) -p \"read_verilog display_lm.v\" >yosys-display_lm.log 2>&1", - "$(YOSYS) -p \"read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc\" >/dev/null 2>&1", - f"$${{CXX:-g++}} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++ >/dev/null 2>&1", - "./yosys-display_lm_cc >yosys-display_lm_cc.log 2>/dev/null", - "grep \"^%l: \\\\\\bot\\$$\" \"yosys-display_lm.log\" >/dev/null 2>&1", - "grep \"^%m: \\\\\\bot\\$$\" \"yosys-display_lm.log\" >/dev/null 2>&1", - "grep \"^%l: \\\\\\bot\\$$\" \"yosys-display_lm_cc.log\" >/dev/null 2>&1", - "grep \"^%m: \\\\\\bot\\$$\" \"yosys-display_lm_cc.log\" >/dev/null 2>&1", + "$(YOSYS) -p \"read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc\"", + f"$${{CXX:-g++}} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++", + "./yosys-display_lm_cc >yosys-display_lm_cc.log", + "grep \"^%l: \\\\\\bot\\$$\" \"yosys-display_lm.log\"", + "grep \"^%m: \\\\\\bot\\$$\" \"yosys-display_lm.log\"", + "grep \"^%l: \\\\\\bot\\$$\" \"yosys-display_lm_cc.log\"", + "grep \"^%m: \\\\\\bot\\$$\" \"yosys-display_lm_cc.log\"", ])) diff --git a/tests/gen_tests_makefile.py b/tests/gen_tests_makefile.py index b81855693..34b9aaedb 100644 --- a/tests/gen_tests_makefile.py +++ b/tests/gen_tests_makefile.py @@ -22,13 +22,13 @@ def generate_target(name, command): print(f"\t@$(call run_test,{target}, $({target}_cmd))") def generate_ys_test(ys_file, yosys_args="", commands=""): - cmd = f'$(YOSYS) -ql {ys_file}.err {yosys_args} {ys_file} >/dev/null 2>&1 && mv {ys_file}.err {ys_file}.log' + cmd = f'$(YOSYS) -ql {ys_file}.err {yosys_args} {ys_file} && mv {ys_file}.err {ys_file}.log' if commands: cmd += f"; \\\n{commands}" generate_target(ys_file, cmd) def generate_tcl_test(tcl_file, yosys_args="", commands=""): - cmd = f'$(YOSYS) -ql {tcl_file}.err {yosys_args} {tcl_file} >/dev/null 2>&1 && mv {tcl_file}.err {tcl_file}.log' + cmd = f'$(YOSYS) -ql {tcl_file}.err {yosys_args} {tcl_file} && mv {tcl_file}.err {tcl_file}.log' if commands: cmd += f"; \\\n{commands}" generate_target(tcl_file, cmd) @@ -37,7 +37,7 @@ def generate_sv_test(sv_file, yosys_args="", commands=""): base = os.path.splitext(sv_file)[0] if not os.path.exists(base + ".ys"): yosys_cmd = '-p "prep -top top; async2sync; sat -enable_undef -verify -prove-asserts"' - cmd = f'$(YOSYS) -ql {sv_file}.err {yosys_cmd} {yosys_args} {sv_file} >/dev/null 2>&1 && mv {sv_file}.err {sv_file}.log' + cmd = f'$(YOSYS) -ql {sv_file}.err {yosys_cmd} {yosys_args} {sv_file} && mv {sv_file}.err {sv_file}.log' if commands: cmd += f"; \\\n{commands}" generate_target(sv_file, cmd) @@ -121,7 +121,7 @@ def generate_custom(callback, extra=None): callback() def generate_autotest_file(test_file, commands): - cmd = f"../tools/autotest.sh -G -j ${{SEEDOPT}} ${{EXTRA_FLAGS}} {test_file} >/dev/null 2>&1; \\\n{commands}" + cmd = f"../tools/autotest.sh -G -j ${{SEEDOPT}} ${{EXTRA_FLAGS}} {test_file}; \\\n{commands}" generate_target(test_file, cmd) def generate_autotest(pattern, extra_flags, cmds=""): diff --git a/tests/liberty/generate_mk.py b/tests/liberty/generate_mk.py index 35bd9335b..64ceec873 100644 --- a/tests/liberty/generate_mk.py +++ b/tests/liberty/generate_mk.py @@ -14,14 +14,14 @@ def lib_tests(): gen_tests_makefile.generate_cmd_test(lib, [ f'$(YOSYS) -p "read_verilog small.v; synth -top small; dfflibmap -info -liberty {lib}" -ql {base}.log;', - f'../../yosys-filterlib - {lib} 2>/dev/null > {lib}.filtered;', + f'../../yosys-filterlib - {lib} > {lib}.filtered;', f'../../yosys-filterlib -verilogsim {lib} > {lib}.verilogsim;', f'diff {lib}.filtered {lib}.filtered.ok;', f'diff {lib}.verilogsim {lib}.verilogsim.ok;', f'if [ -e {base}.log.ok ]; then ' - f'$(YOSYS) -p "dfflibmap -info -liberty {lib}" -TqqQl {base}.log >/dev/null 2>&1; ' + f'$(YOSYS) -p "dfflibmap -info -liberty {lib}" -TqqQl {base}.log; ' f'diff {base}.log {base}.log.ok; ' f'fi', ]) diff --git a/tests/memfile/generate_mk.py b/tests/memfile/generate_mk.py index a40f99ad0..1388961ab 100644 --- a/tests/memfile/generate_mk.py +++ b/tests/memfile/generate_mk.py @@ -10,60 +10,59 @@ def create_tests(): gen_tests_makefile.generate_cmd_test("parent_content1", [ f"{setup};", - '(cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v;', - 'chparam -set MEMFILE \\"content1.dat\\" memory") >/dev/null 2>&1', + 'cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v;', + 'chparam -set MEMFILE \\"content1.dat\\" memory"', ]) gen_tests_makefile.generate_cmd_test("parent_content2_temp", [ f"{setup};", - '(cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v;', - 'chparam -set MEMFILE \\"temp/content2.dat\\" memory") >/dev/null 2>&1', + 'cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v;', + 'chparam -set MEMFILE \\"temp/content2.dat\\" memory"', ]) gen_tests_makefile.generate_cmd_test("parent_content2_full", [ f"{setup};", - '(cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v;', - 'chparam -set MEMFILE \\"memfile/temp/content2.dat\\" memory") >/dev/null 2>&1', + 'cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v;', + 'chparam -set MEMFILE \\"memfile/temp/content2.dat\\" memory"', ]) gen_tests_makefile.generate_cmd_test("same_content1", [ f"{setup};", '$(YOSYS) -qp "read_verilog -defer memory.v;', - 'chparam -set MEMFILE \\"content1.dat\\" memory" >/dev/null 2>&1', + 'chparam -set MEMFILE \\"content1.dat\\" memory"', ]) gen_tests_makefile.generate_cmd_test("same_content2", [ f"{setup};", '$(YOSYS) -qp "read_verilog -defer memory.v;', - 'chparam -set MEMFILE \\"temp/content2.dat\\" memory" >/dev/null 2>&1', + 'chparam -set MEMFILE \\"temp/content2.dat\\" memory"', ]) gen_tests_makefile.generate_cmd_test("child_content1", [ f"{setup};", - '(cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v;', - 'chparam -set MEMFILE \\"content1.dat\\" memory") >/dev/null 2>&1', + 'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v;', + 'chparam -set MEMFILE \\"content1.dat\\" memory"', ]) gen_tests_makefile.generate_cmd_test("child_content2_temp", [ f"{setup};", - '(cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v;', - 'chparam -set MEMFILE \\"temp/content2.dat\\" memory") >/dev/null 2>&1', + 'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v;', + 'chparam -set MEMFILE \\"temp/content2.dat\\" memory"', ]) gen_tests_makefile.generate_cmd_test("child_content2_direct", [ f"{setup};", - '(cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v;', - 'chparam -set MEMFILE \\"temp/content2.dat\\" memory") >/dev/null 2>&1', + 'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v;', + 'chparam -set MEMFILE \\"temp/content2.dat\\" memory"', ]) gen_tests_makefile.generate_cmd_test("fail_empty_filename", - '! $(YOSYS) -qp "read_verilog memory.v" >/dev/null 2>&1') + '! $(YOSYS) -qp "read_verilog memory.v"') gen_tests_makefile.generate_cmd_test("fail_missing_file", [ '! $(YOSYS) -qp "read_verilog -defer memory.v;', - 'chparam -set MEMFILE \\"content3.dat\\" memory" >/dev/null 2>&1', + 'chparam -set MEMFILE \\"content3.dat\\" memory"', ]) extra = ["YOSYS_ABS := $(abspath $(YOSYS))"] gen_tests_makefile.generate_custom(create_tests, extra) - diff --git a/tests/memlib/generate_mk.py b/tests/memlib/generate_mk.py index e91580b7d..5f846a573 100644 --- a/tests/memlib/generate_mk.py +++ b/tests/memlib/generate_mk.py @@ -1577,7 +1577,7 @@ def create_tests(): f"../tools/autotest.sh -G -j ${{SEEDOPT}} ${{EXTRA_FLAGS}} " f"-p 'script ../t_{t.name}.ys'" f"{libs_args} " - f"t_{t.name}.v >/dev/null 2>&1 || (cat t_{t.name}.err; exit 1)" + f"t_{t.name}.v || (cat t_{t.name}.err; exit 1)" ) gen_tests_makefile.generate_target(t.name, cmd) diff --git a/tests/realmath/generate_mk.py b/tests/realmath/generate_mk.py index b56340335..98cb0f186 100644 --- a/tests/realmath/generate_mk.py +++ b/tests/realmath/generate_mk.py @@ -100,8 +100,8 @@ for idx in range(args.count): def create_tests(): for idx in range(args.count): cmd = [ - f"$(YOSYS) -qq uut_{idx:05d}.ys >/dev/null 2>&1 &&", - f"iverilog -o uut_{idx:05d}_tb uut_{idx:05d}_tb.v uut_{idx:05d}.v uut_{idx:05d}_syn.v >/dev/null 2>&1 &&", + f"$(YOSYS) -qq uut_{idx:05d}.ys &&", + f"iverilog -o uut_{idx:05d}_tb uut_{idx:05d}_tb.v uut_{idx:05d}.v uut_{idx:05d}_syn.v &&", f"./uut_{idx:05d}_tb" # f"./uut_{idx:05d}_tb | tee uut_{idx:05d}.err;", # f"if test -s uut_{idx:05d}.err; then", diff --git a/tests/rpc/generate_mk.py b/tests/rpc/generate_mk.py index 95ab05a7d..aca802ebe 100644 --- a/tests/rpc/generate_mk.py +++ b/tests/rpc/generate_mk.py @@ -11,7 +11,7 @@ def create_tests(): for ys in yss: gen_tests_makefile.generate_ys_test(ys) - cmd = [ "python3 frontend.py unix-socket frontend.sock >/dev/null 2>&1" ] + cmd = [ "python3 frontend.py unix-socket frontend.sock" ] gen_tests_makefile.generate_cmd_test("frontend.py", cmd) gen_tests_makefile.generate_custom(create_tests) diff --git a/tests/svinterfaces/generate_mk.py b/tests/svinterfaces/generate_mk.py index e27091e12..7ea337b2b 100644 --- a/tests/svinterfaces/generate_mk.py +++ b/tests/svinterfaces/generate_mk.py @@ -15,17 +15,17 @@ runone_tests = [ def run_one(): for testname in runone_tests: cmd_lines = [ - f'../../yosys -p "read_verilog -sv {testname}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog {testname}_syn.v" >> {testname}.log_stdout 2>> {testname}.log_stderr;', - f'../../yosys -p "read_verilog -sv {testname}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog {testname}_ref_syn.v" >> {testname}.log_stdout 2>> {testname}.log_stderr;', + f'$(YOSYS) -p "read_verilog -sv {testname}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog {testname}_syn.v" >> {testname}.log_stdout 2>> {testname}.log_stderr;', + f'$(YOSYS) -p "read_verilog -sv {testname}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog {testname}_ref_syn.v" >> {testname}.log_stdout 2>> {testname}.log_stderr;', f'rm -f a.out reference_result.txt dut_result.txt;', - f'iverilog -g2012 {testname}_syn.v >/dev/null 2>&1;', - f'iverilog -g2012 {testname}_ref_syn.v >/dev/null 2>&1;', - f'iverilog -g2012 {testname}_tb.v {testname}_ref_syn.v >/dev/null 2>&1;', - f'./a.out >/dev/null 2>&1;', + f'iverilog -g2012 {testname}_syn.v;', + f'iverilog -g2012 {testname}_ref_syn.v;', + f'iverilog -g2012 {testname}_tb.v {testname}_ref_syn.v;', + f'./a.out;', f'mv output.txt reference_result.txt;', - f'iverilog -g2012 {testname}_tb_wrapper.v {testname}_syn.v >/dev/null 2>&1;' if testname=="svinterface_at_top" else - f'iverilog -g2012 {testname}_tb.v {testname}_syn.v >/dev/null 2>&1;', - f'./a.out >/dev/null 2>&1;', + f'iverilog -g2012 {testname}_tb_wrapper.v {testname}_syn.v;' if testname=="svinterface_at_top" else + f'iverilog -g2012 {testname}_tb.v {testname}_syn.v;', + f'./a.out;', f'mv output.txt dut_result.txt;', f'diff reference_result.txt dut_result.txt > {testname}.diff', ]